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style: improve code formatting and readability in asmGenerator

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This commit is contained in:
Guy C 2025-02-24 02:04:21 +00:00
parent dc61b1e390
commit 2bed722a4f
1 changed files with 8 additions and 7 deletions
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15
src/main/wacc/backend/asmGenerator.scala
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@ -96,11 +96,12 @@ object asmGenerator {
val elseLabel = labelGenerator.getLabel()
val endLabel = labelGenerator.getLabel()
evalExprIntoReg(cond, Register(RegSize.R64, RegName.AX)) ++
List(Compare(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
Jump(LabelArg(elseLabel), Cond.Equal)) ++
thenBranch.flatMap(generateStmt) ++
List(Jump(LabelArg(endLabel)),
LabelDef(elseLabel)) ++
List(
Compare(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
Jump(LabelArg(elseLabel), Cond.Equal)
) ++
thenBranch.flatMap(generateStmt) ++
List(Jump(LabelArg(endLabel)), LabelDef(elseLabel)) ++
elseBranch.flatMap(generateStmt) ++
List(LabelDef(endLabel))
}
@ -139,7 +140,7 @@ object asmGenerator {
}
// TODO other expr types
case BoolLiter(v) => List(Move(dest, ImmediateVal(if (v) 1 else 0)))
case _ => List()
case _ => List()
}
}
@ -183,7 +184,7 @@ object asmGenerator {
def funcPrologue(): List[AsmLine] = {
List(
Push(Register(RegSize.R64, RegName.BP)),
Move(Register(RegSize.R64, RegName.BP), Register(RegSize.R64, RegName.SP)),
Move(Register(RegSize.R64, RegName.BP), Register(RegSize.R64, RegName.SP))
)
}