diff --git a/src/main/wacc/backend/asmGenerator.scala b/src/main/wacc/backend/asmGenerator.scala
index 55da169..ec16435 100644
--- a/src/main/wacc/backend/asmGenerator.scala
+++ b/src/main/wacc/backend/asmGenerator.scala
@@ -96,11 +96,12 @@ object asmGenerator {
         val elseLabel = labelGenerator.getLabel()
         val endLabel = labelGenerator.getLabel()
         evalExprIntoReg(cond, Register(RegSize.R64, RegName.AX)) ++
-          List(Compare(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
-               Jump(LabelArg(elseLabel), Cond.Equal)) ++
-               thenBranch.flatMap(generateStmt) ++
-               List(Jump(LabelArg(endLabel)),
-                    LabelDef(elseLabel)) ++
+          List(
+            Compare(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
+            Jump(LabelArg(elseLabel), Cond.Equal)
+          ) ++
+          thenBranch.flatMap(generateStmt) ++
+          List(Jump(LabelArg(endLabel)), LabelDef(elseLabel)) ++
           elseBranch.flatMap(generateStmt) ++
           List(LabelDef(endLabel))
       }
@@ -139,7 +140,7 @@ object asmGenerator {
         }
       // TODO other expr types
       case BoolLiter(v) => List(Move(dest, ImmediateVal(if (v) 1 else 0)))
-      case _ => List()
+      case _            => List()
     }
   }
 
@@ -183,7 +184,7 @@ object asmGenerator {
   def funcPrologue(): List[AsmLine] = {
     List(
       Push(Register(RegSize.R64, RegName.BP)),
-      Move(Register(RegSize.R64, RegName.BP), Register(RegSize.R64, RegName.SP)),
+      Move(Register(RegSize.R64, RegName.BP), Register(RegSize.R64, RegName.SP))
     )
   }