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feat: implement label generation and basic conditional branching in asmGenerator

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This commit is contained in:
Guy C 2025-02-24 02:00:35 +00:00
parent c59c28ecbd
commit dc61b1e390
1 changed files with 21 additions and 2 deletions
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23
src/main/wacc/backend/asmGenerator.scala
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@ -3,6 +3,13 @@ package wacc
import scala.collection.mutable.LinkedHashMap import scala.collection.mutable.LinkedHashMap
import scala.collection.mutable.ListBuffer import scala.collection.mutable.ListBuffer
object labelGenerator {
var labelVal = -1
def getLabel(): String = {
labelVal += 1
s".L$labelVal"
}
}
object asmGenerator { object asmGenerator {
import microWacc._ import microWacc._
import assemblyIR._ import assemblyIR._
@ -85,7 +92,18 @@ object asmGenerator {
evalExprIntoReg(rhs, Register(RegSize.R64, RegName.AX)) ++ evalExprIntoReg(rhs, Register(RegSize.R64, RegName.AX)) ++
List(Move(dest, Register(RegSize.R64, RegName.AX))) List(Move(dest, Register(RegSize.R64, RegName.AX)))
}) })
// TODO other statements case If(cond, thenBranch, elseBranch) => {
val elseLabel = labelGenerator.getLabel()
val endLabel = labelGenerator.getLabel()
evalExprIntoReg(cond, Register(RegSize.R64, RegName.AX)) ++
List(Compare(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
Jump(LabelArg(elseLabel), Cond.Equal)) ++
thenBranch.flatMap(generateStmt) ++
List(Jump(LabelArg(endLabel)),
LabelDef(elseLabel)) ++
elseBranch.flatMap(generateStmt) ++
List(LabelDef(endLabel))
}
case _ => List() case _ => List()
} }
@ -120,6 +138,7 @@ object asmGenerator {
case _ => List() case _ => List()
} }
// TODO other expr types // TODO other expr types
case BoolLiter(v) => List(Move(dest, ImmediateVal(if (v) 1 else 0)))
case _ => List() case _ => List()
} }
} }
@ -165,12 +184,12 @@ object asmGenerator {
List( List(
Push(Register(RegSize.R64, RegName.BP)), Push(Register(RegSize.R64, RegName.BP)),
Move(Register(RegSize.R64, RegName.BP), Register(RegSize.R64, RegName.SP)), Move(Register(RegSize.R64, RegName.BP), Register(RegSize.R64, RegName.SP)),
Move(Register(RegSize.R64, RegName.AX), ImmediateVal(0))
) )
} }
def funcEpilogue(): List[AsmLine] = { def funcEpilogue(): List[AsmLine] = {
List( List(
Move(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
Move(Register(RegSize.R64, RegName.SP), Register(RegSize.R64, RegName.BP)), Move(Register(RegSize.R64, RegName.SP), Register(RegSize.R64, RegName.BP)),
Pop(Register(RegSize.R64, RegName.BP)) Pop(Register(RegSize.R64, RegName.BP))
) )