From dc61b1e390ac4a33e096e96122cf7cf8b1603186 Mon Sep 17 00:00:00 2001
From: Guy C <gc1523@ic.ac.uk>
Date: Mon, 24 Feb 2025 02:00:35 +0000
Subject: [PATCH] feat: implement label generation and basic conditional
 branching in asmGenerator

---
 src/main/wacc/backend/asmGenerator.scala | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/src/main/wacc/backend/asmGenerator.scala b/src/main/wacc/backend/asmGenerator.scala
index df863a7..55da169 100644
--- a/src/main/wacc/backend/asmGenerator.scala
+++ b/src/main/wacc/backend/asmGenerator.scala
@@ -3,6 +3,13 @@ package wacc
 import scala.collection.mutable.LinkedHashMap
 import scala.collection.mutable.ListBuffer
 
+object labelGenerator {
+  var labelVal = -1
+  def getLabel(): String = {
+    labelVal += 1
+    s".L$labelVal"
+  }
+}
 object asmGenerator {
   import microWacc._
   import assemblyIR._
@@ -85,7 +92,18 @@ object asmGenerator {
               evalExprIntoReg(rhs, Register(RegSize.R64, RegName.AX)) ++
                 List(Move(dest, Register(RegSize.R64, RegName.AX)))
           })
-      // TODO other statements
+      case If(cond, thenBranch, elseBranch) => {
+        val elseLabel = labelGenerator.getLabel()
+        val endLabel = labelGenerator.getLabel()
+        evalExprIntoReg(cond, Register(RegSize.R64, RegName.AX)) ++
+          List(Compare(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
+               Jump(LabelArg(elseLabel), Cond.Equal)) ++
+               thenBranch.flatMap(generateStmt) ++
+               List(Jump(LabelArg(endLabel)),
+                    LabelDef(elseLabel)) ++
+          elseBranch.flatMap(generateStmt) ++
+          List(LabelDef(endLabel))
+      }
       case _ => List()
     }
 
@@ -120,6 +138,7 @@ object asmGenerator {
           case _ => List()
         }
       // TODO other expr types
+      case BoolLiter(v) => List(Move(dest, ImmediateVal(if (v) 1 else 0)))
       case _ => List()
     }
   }
@@ -165,12 +184,12 @@ object asmGenerator {
     List(
       Push(Register(RegSize.R64, RegName.BP)),
       Move(Register(RegSize.R64, RegName.BP), Register(RegSize.R64, RegName.SP)),
-      Move(Register(RegSize.R64, RegName.AX), ImmediateVal(0))
     )
   }
 
   def funcEpilogue(): List[AsmLine] = {
     List(
+      Move(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
       Move(Register(RegSize.R64, RegName.SP), Register(RegSize.R64, RegName.BP)),
       Pop(Register(RegSize.R64, RegName.BP))
     )