fix: variable-sized values, heap-allocated arrays (and printCharArray)
This commit is contained in:
parent
691d989b92
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GPG Key ID:
15E168A8B332382C
@ -1,6 +1,7 @@
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package wacc
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import scala.collection.mutable
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import cats.data.Chain
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import parsley.{Failure, Success}
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import scopt.OParser
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import java.io.File
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@ -63,7 +64,7 @@ def frontend(
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}
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val s = "enter an integer to echo"
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def backend(typedProg: microWacc.Program): List[asm.AsmLine] =
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def backend(typedProg: microWacc.Program): Chain[asm.AsmLine] =
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asmGenerator.generateAsm(typedProg)
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def compile(filename: String, outFile: Option[File] = None)(using
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@ -1,37 +1,48 @@
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package wacc
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import scala.collection.mutable.LinkedHashMap
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import cats.data.Chain
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class Stack {
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import assemblyIR._
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import assemblyIR.Size._
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import sizeExtensions.size
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import microWacc as mw
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private val RSP = Register(Size.Q64, RegName.SP)
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private val RSP = Register(Q64, RegName.SP)
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private class StackValue(val size: Size, val offset: Int) {
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def bottom: Int = offset + size.toInt
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def bottom: Int = offset + elemBytes
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}
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private val stack = LinkedHashMap[mw.Expr | Int, StackValue]()
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private val elemBytes: Int = Q64.toInt
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private def sizeBytes: Int = stack.size * elemBytes
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/** The stack's size in bytes. */
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def size: Int = if stack.isEmpty then 0 else stack.last._2.bottom
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def size: Int = stack.size
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/** Push an expression onto the stack. */
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def push(expr: mw.Expr, src: Register): AsmLine = {
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stack += expr -> StackValue(src.size, size)
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stack += expr -> StackValue(src.size, sizeBytes)
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Push(src)
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}
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/** Push an arbitrary register onto the stack. */
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def push(src: Register): AsmLine = {
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stack += stack.size -> StackValue(src.size, size)
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Push(src)
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/** Push a value onto the stack. */
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def push(itemSize: Size, addr: Src): AsmLine = {
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stack += stack.size -> StackValue(itemSize, sizeBytes)
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Push(addr)
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}
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/** Reserve space for a variable on the stack. */
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def reserve(ident: mw.Ident): AsmLine = {
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stack += ident -> StackValue(ident.ty.size, size)
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Subtract(RSP, ImmediateVal(ident.ty.size.toInt))
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stack += ident -> StackValue(ident.ty.size, sizeBytes)
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Subtract(RSP, ImmediateVal(elemBytes))
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}
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/** Reserve space for a register on the stack. */
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def reserve(src: Register): AsmLine = {
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stack += stack.size -> StackValue(src.size, sizeBytes)
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Subtract(RSP, ImmediateVal(src.size.toInt))
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}
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/** Reserve space for values on the stack.
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@ -40,45 +51,40 @@ class Stack {
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* The sizes of the values to reserve space for.
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*/
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def reserve(sizes: List[Size]): AsmLine = {
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val totalSize = sizes
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.map(itemSize =>
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stack += stack.size -> StackValue(itemSize, size)
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itemSize.toInt
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)
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.sum
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Subtract(RSP, ImmediateVal(totalSize))
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sizes.foreach { itemSize =>
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stack += stack.size -> StackValue(itemSize, sizeBytes)
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}
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Subtract(RSP, ImmediateVal(elemBytes * sizes.size))
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}
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/** Pop a value from the stack into a register. Sizes MUST match. */
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def pop(dest: Register): AsmLine = {
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if (dest.size != stack.last._2.size) {
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throw new IllegalArgumentException(
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s"Cannot pop ${stack.last._2.size} bytes into $dest (${dest.size} bytes) register"
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)
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}
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stack.remove(stack.last._1)
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Pop(dest)
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}
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/** Drop the top n values from the stack. */
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def drop(n: Int = 1): AsmLine = {
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val totalSize = (1 to n)
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.map(_ =>
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val itemSize = stack.last._2.size.toInt
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stack.remove(stack.last._1)
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itemSize
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)
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.sum
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Add(RSP, ImmediateVal(totalSize))
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(1 to n).foreach { _ =>
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stack.remove(stack.last._1)
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}
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Add(RSP, ImmediateVal(n * elemBytes))
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}
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/** Get a lazy IndexAddress for a variable in the stack. */
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def accessVar(ident: mw.Ident): () => IndexAddress = () => {
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IndexAddress(RSP, stack.size - stack(ident).bottom)
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/** Generate AsmLines within a scope, which is reset after the block. */
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def withScope(block: () => Chain[AsmLine]): Chain[AsmLine] = {
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val resetToSize = stack.size
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var lines = block()
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lines :+= drop(stack.size - resetToSize)
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lines
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}
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/** Get an IndexAddress for a variable in the stack. */
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def accessVar(ident: mw.Ident): IndexAddress =
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IndexAddress(RSP, sizeBytes - stack(ident).bottom)
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def contains(ident: mw.Ident): Boolean = stack.contains(ident)
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def head: MemLocation = MemLocation(RSP)
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def head(offset: Size): MemLocation = MemLocation(RSP, Some(offset))
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// TODO: Might want to actually properly handle this with the LinkedHashMap too
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def align(): AsmLine = And(RSP, ImmediateVal(-16))
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def head: MemLocation = MemLocation(RSP, stack.last._2.size)
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override def toString(): String = stack.toString
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}
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@ -1,6 +1,5 @@
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package wacc
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import scala.collection.mutable.LinkedHashMap
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import scala.collection.mutable.ListBuffer
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import cats.data.Chain
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import cats.syntax.foldable._
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@ -8,7 +7,10 @@ import cats.syntax.foldable._
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object asmGenerator {
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import microWacc._
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import assemblyIR._
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import wacc.types._
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import assemblyIR.Size._
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import assemblyIR.RegName._
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import types._
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import sizeExtensions._
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import lexer.escapedChars
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abstract case class Error() {
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@ -29,26 +31,22 @@ object asmGenerator {
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def errLabel = ".L._errDivZero"
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}
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val RAX = Register(RegSize.R64, RegName.AX)
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val EAX = Register(RegSize.E32, RegName.AX)
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val ESP = Register(RegSize.E32, RegName.SP)
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val EDX = Register(RegSize.E32, RegName.DX)
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val RDI = Register(RegSize.R64, RegName.DI)
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val RIP = Register(RegSize.R64, RegName.IP)
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val RBP = Register(RegSize.R64, RegName.BP)
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val RSI = Register(RegSize.R64, RegName.SI)
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val RDX = Register(RegSize.R64, RegName.DX)
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val RCX = Register(RegSize.R64, RegName.CX)
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val R8 = Register(RegSize.R64, RegName.Reg8)
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val R9 = Register(RegSize.R64, RegName.Reg9)
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val argRegs = List(RDI, RSI, RDX, RCX, R8, R9)
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private val RAX = Register(Q64, AX)
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private val EAX = Register(D32, AX)
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private val RDI = Register(Q64, DI)
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private val RIP = Register(Q64, IP)
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private val RBP = Register(Q64, BP)
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private val RSI = Register(Q64, SI)
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private val RDX = Register(Q64, DX)
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private val RCX = Register(Q64, CX)
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private val argRegs = List(DI, SI, DX, CX, R8, R9)
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val _8_BIT_MASK = 0xff
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private val _8_BIT_MASK = 0xff
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extension (chain: Chain[AsmLine])
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def +(line: AsmLine): Chain[AsmLine] = chain.append(line)
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extension [T](chain: Chain[T])
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def +(item: T): Chain[T] = chain.append(item)
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def concatAll(chains: Chain[AsmLine]*): Chain[AsmLine] =
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def concatAll(chains: Chain[T]*): Chain[T] =
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chains.foldLeft(chain)(_ ++ _)
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class LabelGenerator {
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@ -63,7 +61,7 @@ object asmGenerator {
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}
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}
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def generateAsm(microProg: Program): List[AsmLine] = {
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def generateAsm(microProg: Program): Chain[AsmLine] = {
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given stack: Stack = Stack()
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given strings: ListBuffer[String] = ListBuffer[String]()
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given labelGenerator: LabelGenerator = LabelGenerator()
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@ -71,7 +69,6 @@ object asmGenerator {
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val progAsm = Chain(LabelDef("main")).concatAll(
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funcPrologue(),
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Chain.one(stack.align()),
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main.foldMap(generateStmt(_)),
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Chain.one(Xor(RAX, RAX)),
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funcEpilogue(),
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@ -95,12 +92,10 @@ object asmGenerator {
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strDirs,
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Chain.one(Directive.Text),
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progAsm
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).toList
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)
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}
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private def wrapBuiltinFunc(labelName: String, funcBody: Chain[AsmLine])(using
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stack: Stack
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): Chain[AsmLine] = {
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private def wrapBuiltinFunc(labelName: String, funcBody: Chain[AsmLine]): Chain[AsmLine] = {
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var chain = Chain.one[AsmLine](LabelDef(labelName))
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chain ++= funcPrologue()
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chain ++= funcBody
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@ -108,7 +103,7 @@ object asmGenerator {
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chain
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}
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def generateUserFunc(func: FuncDecl)(using
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private def generateUserFunc(func: FuncDecl)(using
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strings: ListBuffer[String],
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labelGenerator: LabelGenerator
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): Chain[AsmLine] = {
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@ -119,29 +114,27 @@ object asmGenerator {
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chain ++= funcPrologue()
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// Push the rest of params onto the stack for simplicity
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argRegs.zip(func.params).foreach { (reg, param) =>
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chain += stack.push(param, reg)
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chain += stack.push(param, Register(Q64, reg))
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}
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chain ++= func.body.foldMap(generateStmt(_))
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// No need for epilogue here since all user functions must return explicitly
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chain
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}
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def generateBuiltInFuncs()(using
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stack: Stack,
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strings: ListBuffer[String],
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private def generateBuiltInFuncs()(using
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labelGenerator: LabelGenerator
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): Chain[AsmLine] = {
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var chain = Chain.empty[AsmLine]
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chain ++= wrapBuiltinFunc(
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labelGenerator.getLabel(Builtin.Exit),
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Chain(stack.align(), assemblyIR.Call(CLibFunc.Exit))
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Chain(stackAlign, assemblyIR.Call(CLibFunc.Exit))
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)
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chain ++= wrapBuiltinFunc(
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labelGenerator.getLabel(Builtin.Printf),
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Chain(
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stack.align(),
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stackAlign,
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assemblyIR.Call(CLibFunc.PrintF),
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Xor(RDI, RDI),
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assemblyIR.Call(CLibFunc.Fflush)
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@ -151,9 +144,9 @@ object asmGenerator {
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chain ++= wrapBuiltinFunc(
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labelGenerator.getLabel(Builtin.PrintCharArray),
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Chain(
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stack.align(),
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Load(RDX, IndexAddress(RSI, 8)),
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Move(RSI, MemLocation(RSI)),
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stackAlign,
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Load(RDX, IndexAddress(RSI, KnownType.Int.size.toInt)),
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Move(Register(D32, SI), MemLocation(RSI, D32)),
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assemblyIR.Call(CLibFunc.PrintF),
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Xor(RDI, RDI),
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assemblyIR.Call(CLibFunc.Fflush)
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@ -162,7 +155,7 @@ object asmGenerator {
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chain ++= wrapBuiltinFunc(
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labelGenerator.getLabel(Builtin.Malloc),
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Chain(stack.align(), assemblyIR.Call(CLibFunc.Malloc))
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Chain(stackAlign, assemblyIR.Call(CLibFunc.Malloc))
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// Out of memory check is optional
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)
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@ -171,13 +164,12 @@ object asmGenerator {
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chain ++= wrapBuiltinFunc(
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labelGenerator.getLabel(Builtin.Read),
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Chain(
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stack.align(),
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stack.reserve(),
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stack.push(RSI),
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Load(RSI, stack.head),
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stackAlign,
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Subtract(Register(Q64, SP), ImmediateVal(8)),
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Push(RSI),
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Load(RSI, MemLocation(Register(Q64, SP), Q64)),
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assemblyIR.Call(CLibFunc.Scanf),
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stack.pop(RAX),
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stack.drop()
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Pop(RAX)
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)
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)
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@ -185,7 +177,7 @@ object asmGenerator {
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// TODO can this be done with a call to generateStmt?
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// Consider other error cases -> look to generalise
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LabelDef(zeroDivError.errLabel),
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stack.align(),
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stackAlign,
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Load(RDI, IndexAddress(RIP, LabelArg(zeroDivError.strLabel))),
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assemblyIR.Call(CLibFunc.PrintF),
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Move(RDI, ImmediateVal(-1)),
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@ -195,53 +187,33 @@ object asmGenerator {
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chain
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}
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/** Wraps a chain in a stack reset.
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*
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* This is useful for ensuring that the stack size at the death of scope is the same as the stack
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* size at the start of the scope. See branching (If / While)
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*
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* @param genChain
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* Function that generates the scope AsmLines
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* @param stack
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* The stack to reset
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* @return
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* The generated scope AsmLines
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*/
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private def generateScope(genChain: () => Chain[AsmLine])(using
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stack: Stack
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): Chain[AsmLine] = {
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val stackSizeStart = stack.size
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var chain = genChain()
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chain += stack.drop(stack.size - stackSizeStart)
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chain
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}
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def generateStmt(stmt: Stmt)(using
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private def generateStmt(stmt: Stmt)(using
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stack: Stack,
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strings: ListBuffer[String],
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labelGenerator: LabelGenerator
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): Chain[AsmLine] = {
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var chain = Chain.empty[AsmLine]
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chain += Comment(stmt.toString)
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stmt match {
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case Assign(lhs, rhs) =>
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lhs match {
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case ident: Ident =>
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val dest = stack.accessVar(ident)
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if (!stack.contains(ident)) chain += stack.reserve(ident)
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chain ++= evalExprOntoStack(rhs)
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chain += stack.pop(RDX)
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chain += Move(dest(), RDX)
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chain += stack.pop(RAX)
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chain += Move(stack.accessVar(ident), RAX)
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case ArrayElem(x, i) =>
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chain ++= evalExprOntoStack(x)
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chain ++= evalExprOntoStack(i)
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chain ++= evalExprOntoStack(rhs)
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chain ++= evalExprOntoStack(i)
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chain ++= evalExprOntoStack(x)
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chain += stack.pop(RAX)
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chain += stack.pop(RCX)
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chain += stack.pop(RDX)
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chain += Move(IndexAddress(RDX, 8, RCX, 8), RAX)
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chain += Move(
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IndexAddress(RAX, KnownType.Int.size.toInt, RCX, x.ty.elemSize.toInt),
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Register(x.ty.elemSize, DX)
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)
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}
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case If(cond, thenBranch, elseBranch) =>
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@ -253,11 +225,11 @@ object asmGenerator {
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chain += Compare(RAX, ImmediateVal(0))
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chain += Jump(LabelArg(elseLabel), Cond.Equal)
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chain ++= generateScope(() => thenBranch.foldMap(generateStmt))
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chain ++= stack.withScope(() => thenBranch.foldMap(generateStmt))
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chain += Jump(LabelArg(endLabel))
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chain += LabelDef(elseLabel)
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chain ++= generateScope(() => elseBranch.foldMap(generateStmt))
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chain ++= stack.withScope(() => elseBranch.foldMap(generateStmt))
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chain += LabelDef(endLabel)
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case While(cond, body) =>
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@ -270,7 +242,7 @@ object asmGenerator {
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chain += Compare(RAX, ImmediateVal(0))
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chain += Jump(LabelArg(endLabel), Cond.Equal)
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chain ++= generateScope(() => body.foldMap(generateStmt))
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chain ++= stack.withScope(() => body.foldMap(generateStmt))
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chain += Jump(LabelArg(startLabel))
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chain += LabelDef(endLabel)
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@ -291,7 +263,7 @@ object asmGenerator {
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chain
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}
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def evalExprOntoStack(expr: Expr)(using
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private def evalExprOntoStack(expr: Expr)(using
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stack: Stack,
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strings: ListBuffer[String],
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labelGenerator: LabelGenerator
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@ -299,111 +271,117 @@ object asmGenerator {
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var chain = Chain.empty[AsmLine]
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val stackSizeStart = stack.size
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expr match {
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case IntLiter(v) => chain += stack.push(ImmediateVal(v))
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case CharLiter(v) => chain += stack.push(ImmediateVal(v.toInt))
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case ident: Ident => chain += stack.push(stack.accessVar(ident)())
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case IntLiter(v) => chain += stack.push(KnownType.Int.size, ImmediateVal(v))
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case CharLiter(v) => chain += stack.push(KnownType.Char.size, ImmediateVal(v.toInt))
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case ident: Ident => chain += stack.push(ident.ty.size, stack.accessVar(ident))
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case ArrayLiter(elems) =>
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case array @ ArrayLiter(elems) =>
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expr.ty match {
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case KnownType.String =>
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strings += elems.collect { case CharLiter(v) => v }.mkString
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chain += Load(RAX, IndexAddress(RIP, LabelArg(s".L.str${strings.size - 1}")))
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chain += stack.push(RAX)
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case _ =>
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chain += stack.push(Q64, RAX)
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case ty =>
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chain ++= generateCall(
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microWacc.Call(Builtin.Malloc, List(IntLiter((elems.size + 1) * 8))),
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microWacc.Call(Builtin.Malloc, List(IntLiter(array.heapSize))),
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isTail = false
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)
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chain += stack.push(RAX)
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chain += stack.push(Q64, RAX)
|
||||
// Store the length of the array at the start
|
||||
chain += Move(MemLocation(RAX, SizeDir.DWord), ImmediateVal(elems.size))
|
||||
chain += Move(MemLocation(RAX, D32), ImmediateVal(elems.size))
|
||||
elems.zipWithIndex.foldMap { (elem, i) =>
|
||||
chain ++= evalExprOntoStack(elem)
|
||||
chain += stack.pop(RCX)
|
||||
chain += stack.pop(RAX)
|
||||
chain += Move(IndexAddress(RAX, 8 * (i + 1)), RCX)
|
||||
chain += stack.push(RAX)
|
||||
chain += Move(IndexAddress(RAX, 4 + i * ty.elemSize.toInt), Register(ty.elemSize, CX))
|
||||
chain += stack.push(Q64, RAX)
|
||||
}
|
||||
}
|
||||
|
||||
case BoolLiter(true) => chain += stack.push(ImmediateVal(1))
|
||||
case BoolLiter(true) =>
|
||||
chain += stack.push(KnownType.Bool.size, ImmediateVal(1))
|
||||
case BoolLiter(false) =>
|
||||
chain += Xor(RAX, RAX)
|
||||
chain += stack.push(RAX)
|
||||
case NullLiter() => chain += stack.push(ImmediateVal(0))
|
||||
chain += stack.push(KnownType.Bool.size, RAX)
|
||||
case NullLiter() =>
|
||||
chain += stack.push(KnownType.Pair(?, ?).size, ImmediateVal(0))
|
||||
case ArrayElem(x, i) =>
|
||||
chain ++= evalExprOntoStack(x)
|
||||
chain ++= evalExprOntoStack(i)
|
||||
chain += stack.pop(RCX)
|
||||
chain += stack.pop(RAX)
|
||||
// + 1 because we store the length of the array at the start
|
||||
chain += stack.push(IndexAddress(RAX, 8, RCX, 8))
|
||||
// + Int because we store the length of the array at the start
|
||||
chain += Move(
|
||||
Register(x.ty.elemSize, AX),
|
||||
IndexAddress(RAX, KnownType.Int.size.toInt, RCX, x.ty.elemSize.toInt)
|
||||
)
|
||||
chain += stack.push(x.ty.elemSize, RAX)
|
||||
case UnaryOp(x, op) =>
|
||||
chain ++= evalExprOntoStack(x)
|
||||
op match {
|
||||
case UnaryOperator.Chr | UnaryOperator.Ord => // No op needed
|
||||
case UnaryOperator.Len =>
|
||||
// Access the elem
|
||||
case UnaryOperator.Len =>
|
||||
chain += stack.pop(RAX)
|
||||
chain += Push(MemLocation(RAX))
|
||||
case UnaryOperator.Negate => chain += Negate(stack.head(SizeDir.DWord))
|
||||
chain += Move(EAX, MemLocation(RAX, D32))
|
||||
chain += stack.push(D32, RAX)
|
||||
case UnaryOperator.Negate =>
|
||||
chain += Negate(stack.head)
|
||||
case UnaryOperator.Not =>
|
||||
chain += Xor(stack.head(SizeDir.DWord), ImmediateVal(1))
|
||||
chain += Xor(stack.head, ImmediateVal(1))
|
||||
}
|
||||
|
||||
case BinaryOp(x, y, op) =>
|
||||
val destX = Register(x.ty.size, AX)
|
||||
chain ++= evalExprOntoStack(y)
|
||||
chain ++= evalExprOntoStack(x)
|
||||
|
||||
chain += stack.pop(RAX)
|
||||
|
||||
op match {
|
||||
case BinaryOperator.Add => chain += Add(stack.head(SizeDir.DWord), EAX)
|
||||
case BinaryOperator.Add =>
|
||||
chain += Add(stack.head, destX)
|
||||
case BinaryOperator.Sub =>
|
||||
chain += Subtract(EAX, stack.head(SizeDir.DWord))
|
||||
chain += Subtract(destX, stack.head)
|
||||
chain += stack.drop()
|
||||
chain += stack.push(RAX)
|
||||
chain += stack.push(destX.size, RAX)
|
||||
case BinaryOperator.Mul =>
|
||||
chain += Multiply(EAX, stack.head(SizeDir.DWord))
|
||||
chain += Multiply(destX, stack.head)
|
||||
chain += stack.drop()
|
||||
chain += stack.push(RAX)
|
||||
chain += stack.push(destX.size, RAX)
|
||||
|
||||
case BinaryOperator.Div =>
|
||||
chain += Compare(stack.head(SizeDir.DWord), ImmediateVal(0))
|
||||
chain += Compare(stack.head, ImmediateVal(0))
|
||||
chain += Jump(LabelArg(zeroDivError.errLabel), Cond.Equal)
|
||||
chain += CDQ()
|
||||
chain += Divide(stack.head(SizeDir.DWord))
|
||||
chain += Divide(stack.head)
|
||||
chain += stack.drop()
|
||||
chain += stack.push(RAX)
|
||||
chain += stack.push(destX.size, RAX)
|
||||
|
||||
case BinaryOperator.Mod =>
|
||||
chain += CDQ()
|
||||
chain += Divide(stack.head(SizeDir.DWord))
|
||||
chain += Divide(stack.head)
|
||||
chain += stack.drop()
|
||||
chain += stack.push(RDX)
|
||||
chain += stack.push(destX.size, RDX)
|
||||
|
||||
case BinaryOperator.Eq => chain ++= generateComparison(Cond.Equal)
|
||||
case BinaryOperator.Neq => chain ++= generateComparison(Cond.NotEqual)
|
||||
case BinaryOperator.Greater => chain ++= generateComparison(Cond.Greater)
|
||||
case BinaryOperator.GreaterEq => chain ++= generateComparison(Cond.GreaterEqual)
|
||||
case BinaryOperator.Less => chain ++= generateComparison(Cond.Less)
|
||||
case BinaryOperator.LessEq => chain ++= generateComparison(Cond.LessEqual)
|
||||
case BinaryOperator.And => chain += And(stack.head(SizeDir.DWord), EAX)
|
||||
case BinaryOperator.Or => chain += Or(stack.head(SizeDir.DWord), EAX)
|
||||
case BinaryOperator.Eq => chain ++= generateComparison(destX, Cond.Equal)
|
||||
case BinaryOperator.Neq => chain ++= generateComparison(destX, Cond.NotEqual)
|
||||
case BinaryOperator.Greater => chain ++= generateComparison(destX, Cond.Greater)
|
||||
case BinaryOperator.GreaterEq => chain ++= generateComparison(destX, Cond.GreaterEqual)
|
||||
case BinaryOperator.Less => chain ++= generateComparison(destX, Cond.Less)
|
||||
case BinaryOperator.LessEq => chain ++= generateComparison(destX, Cond.LessEqual)
|
||||
case BinaryOperator.And => chain += And(stack.head, destX)
|
||||
case BinaryOperator.Or => chain += Or(stack.head, destX)
|
||||
}
|
||||
|
||||
case call: microWacc.Call =>
|
||||
chain ++= generateCall(call, isTail = false)
|
||||
chain += stack.push(RAX)
|
||||
chain += stack.push(call.ty.size, RAX)
|
||||
}
|
||||
|
||||
if chain.isEmpty then chain += stack.push(ImmediateVal(0))
|
||||
|
||||
assert(stack.size == stackSizeStart + 1)
|
||||
chain
|
||||
}
|
||||
|
||||
def generateCall(call: microWacc.Call, isTail: Boolean)(using
|
||||
private def generateCall(call: microWacc.Call, isTail: Boolean)(using
|
||||
stack: Stack,
|
||||
strings: ListBuffer[String],
|
||||
labelGenerator: LabelGenerator
|
||||
@ -413,7 +391,7 @@ object asmGenerator {
|
||||
|
||||
argRegs.zip(args).foldMap { (reg, expr) =>
|
||||
chain ++= evalExprOntoStack(expr)
|
||||
chain += stack.pop(reg)
|
||||
chain += stack.pop(Register(Q64, reg))
|
||||
}
|
||||
|
||||
args.drop(argRegs.size).foldMap {
|
||||
@ -434,77 +412,36 @@ object asmGenerator {
|
||||
chain
|
||||
}
|
||||
|
||||
def generateComparison(cond: Cond)(using
|
||||
stack: Stack,
|
||||
strings: ListBuffer[String],
|
||||
labelGenerator: LabelGenerator
|
||||
private def generateComparison(destX: Register, cond: Cond)(using
|
||||
stack: Stack
|
||||
): Chain[AsmLine] = {
|
||||
var chain = Chain.empty[AsmLine]
|
||||
|
||||
chain += Compare(EAX, stack.head(SizeDir.DWord))
|
||||
chain += Set(Register(RegSize.Byte, RegName.AL), cond)
|
||||
chain += Compare(destX, stack.head)
|
||||
chain += Set(Register(B8, AX), cond)
|
||||
chain += And(RAX, ImmediateVal(_8_BIT_MASK))
|
||||
chain += stack.drop()
|
||||
chain += stack.push(RAX)
|
||||
chain += stack.push(B8, RAX)
|
||||
|
||||
chain
|
||||
}
|
||||
|
||||
// Missing a sub instruction but dont think we need it
|
||||
def funcPrologue()(using stack: Stack): Chain[AsmLine] = {
|
||||
private def funcPrologue(): Chain[AsmLine] = {
|
||||
var chain = Chain.empty[AsmLine]
|
||||
chain += stack.push(RBP)
|
||||
chain += Move(RBP, Register(RegSize.R64, RegName.SP))
|
||||
chain += Push(RBP)
|
||||
chain += Move(RBP, Register(Q64, SP))
|
||||
chain
|
||||
}
|
||||
|
||||
def funcEpilogue()(using stack: Stack): Chain[AsmLine] = {
|
||||
private def funcEpilogue(): Chain[AsmLine] = {
|
||||
var chain = Chain.empty[AsmLine]
|
||||
chain += Move(Register(RegSize.R64, RegName.SP), RBP)
|
||||
chain += Move(Register(Q64, SP), RBP)
|
||||
chain += Pop(RBP)
|
||||
chain += assemblyIR.Return()
|
||||
chain
|
||||
}
|
||||
|
||||
class Stack {
|
||||
private val stack = LinkedHashMap[Expr | Int, Int]()
|
||||
private val RSP = Register(RegSize.R64, RegName.SP)
|
||||
|
||||
private def next: Int = stack.size + 1
|
||||
def size: Int = stack.size
|
||||
def push(expr: Expr, src: Src): AsmLine = {
|
||||
stack += expr -> next
|
||||
Push(src)
|
||||
}
|
||||
def push(src: Src): AsmLine = {
|
||||
stack += stack.size -> next
|
||||
Push(src)
|
||||
}
|
||||
def pop(dest: Src): AsmLine = {
|
||||
stack.remove(stack.last._1)
|
||||
Pop(dest)
|
||||
}
|
||||
def reserve(ident: Ident): AsmLine = {
|
||||
stack += ident -> next
|
||||
Subtract(RSP, ImmediateVal(8))
|
||||
}
|
||||
def reserve(n: Int = 1): AsmLine = {
|
||||
(1 to n).foreach(_ => stack += stack.size -> next)
|
||||
Subtract(RSP, ImmediateVal(n * 8))
|
||||
}
|
||||
def drop(n: Int = 1): AsmLine = {
|
||||
(1 to n).foreach(_ => stack.remove(stack.last._1))
|
||||
Add(RSP, ImmediateVal(n * 8))
|
||||
}
|
||||
def accessVar(ident: Ident): () => IndexAddress = () => {
|
||||
IndexAddress(RSP, (stack.size - stack(ident)) * 8)
|
||||
}
|
||||
def head: MemLocation = MemLocation(RSP)
|
||||
def head(size: SizeDir): MemLocation = MemLocation(RSP, size)
|
||||
def contains(ident: Ident): Boolean = stack.contains(ident)
|
||||
// TODO: Might want to actually properly handle this with the LinkedHashMap too
|
||||
def align(): AsmLine = And(RSP, ImmediateVal(-16))
|
||||
}
|
||||
private def stackAlign: AsmLine = And(Register(Q64, SP), ImmediateVal(-16))
|
||||
|
||||
private val escapedCharsMapping = escapedChars.map { case (k, v) => v -> s"\\$k" }
|
||||
extension (s: String) {
|
||||
|
||||
@ -97,11 +97,9 @@ object assemblyIR {
|
||||
}
|
||||
}
|
||||
|
||||
case class MemLocation(pointer: Register, opSize: Option[Size] = None) extends Dest with Src {
|
||||
def this(pointer: Register, opSize: Size) = this(pointer, Some(opSize))
|
||||
|
||||
case class MemLocation(pointer: Register, opSize: Size) extends Dest with Src {
|
||||
override def toString =
|
||||
opSize.getOrElse("").toString + s"[$pointer]"
|
||||
opSize.toString + s"[$pointer]"
|
||||
}
|
||||
|
||||
// TODO to string is wacky
|
||||
|
||||
@ -11,8 +11,8 @@ object sizeExtensions {
|
||||
def heapSize: Int = (expr, expr.ty) match {
|
||||
case (ArrayLiter(elems), KnownType.Array(KnownType.Char)) =>
|
||||
KnownType.Int.size.toInt + elems.size.toInt * KnownType.Char.size.toInt
|
||||
case (ArrayLiter(elems), _) =>
|
||||
KnownType.Int.size.toInt + elems.map(_.ty.size.toInt).sum
|
||||
case (ArrayLiter(elems), ty) =>
|
||||
KnownType.Int.size.toInt + elems.size * ty.elemSize.toInt
|
||||
case _ => expr.ty.size.toInt
|
||||
}
|
||||
}
|
||||
@ -25,5 +25,11 @@ object sizeExtensions {
|
||||
case KnownType.Bool | KnownType.Char => Size.B8
|
||||
case KnownType.String | KnownType.Array(_) | KnownType.Pair(_, _) | ? => Size.Q64
|
||||
}
|
||||
|
||||
def elemSize: Size = ty match {
|
||||
case KnownType.Array(elem) => elem.size
|
||||
case KnownType.Pair(_, _) => Size.Q64
|
||||
case _ => ty.size
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,11 +1,12 @@
|
||||
package wacc
|
||||
|
||||
import java.io.PrintStream
|
||||
import cats.data.Chain
|
||||
|
||||
object writer {
|
||||
import assemblyIR._
|
||||
|
||||
def writeTo(asmList: List[AsmLine], printStream: PrintStream): Unit = {
|
||||
asmList.foreach(printStream.println)
|
||||
def writeTo(asmList: Chain[AsmLine], printStream: PrintStream): Unit = {
|
||||
asmList.iterator.foreach(printStream.println)
|
||||
}
|
||||
}
|
||||
|
||||
@ -223,10 +223,10 @@ object typeChecker {
|
||||
case KnownType.Int => "%d"
|
||||
case KnownType.Pair(_, _) | KnownType.Array(_) | ? => "%p"
|
||||
}
|
||||
val printfCall = { (value: microWacc.Expr) =>
|
||||
val printfCall = { (func: microWacc.Builtin, value: microWacc.Expr) =>
|
||||
List(
|
||||
microWacc.Call(
|
||||
microWacc.Builtin.Printf,
|
||||
func,
|
||||
List(
|
||||
s"$exprFormat${if newline then "\n" else ""}".toMicroWaccCharArray,
|
||||
value
|
||||
@ -239,11 +239,13 @@ object typeChecker {
|
||||
List(
|
||||
microWacc.If(
|
||||
exprTyped,
|
||||
printfCall("true".toMicroWaccCharArray),
|
||||
printfCall("false".toMicroWaccCharArray)
|
||||
printfCall(microWacc.Builtin.Printf, "true".toMicroWaccCharArray),
|
||||
printfCall(microWacc.Builtin.Printf, "false".toMicroWaccCharArray)
|
||||
)
|
||||
)
|
||||
case _ => printfCall(exprTyped)
|
||||
case KnownType.Array(KnownType.Char) =>
|
||||
printfCall(microWacc.Builtin.PrintCharArray, exprTyped)
|
||||
case _ => printfCall(microWacc.Builtin.Printf, exprTyped)
|
||||
}
|
||||
case ast.If(cond, thenStmt, elseStmt) =>
|
||||
List(
|
||||
|
||||
@ -1,42 +1,38 @@
|
||||
import org.scalatest.funsuite.AnyFunSuite
|
||||
import wacc.assemblyIR._
|
||||
import wacc.assemblyIR.Size._
|
||||
import wacc.assemblyIR.RegName._
|
||||
|
||||
class instructionSpec extends AnyFunSuite {
|
||||
|
||||
val named64BitRegister = Register(RegSize.R64, RegName.AX)
|
||||
val named64BitRegister = Register(Q64, AX)
|
||||
|
||||
test("named 64-bit register toString") {
|
||||
assert(named64BitRegister.toString == "rax")
|
||||
}
|
||||
|
||||
val named32BitRegister = Register(RegSize.E32, RegName.AX)
|
||||
val named32BitRegister = Register(D32, AX)
|
||||
|
||||
test("named 32-bit register toString") {
|
||||
assert(named32BitRegister.toString == "eax")
|
||||
}
|
||||
|
||||
val scratch64BitRegister = Register(RegSize.R64, RegName.Reg8)
|
||||
val scratch64BitRegister = Register(Q64, R8)
|
||||
|
||||
test("scratch 64-bit register toString") {
|
||||
assert(scratch64BitRegister.toString == "r8")
|
||||
}
|
||||
|
||||
val scratch32BitRegister = Register(RegSize.E32, RegName.Reg8)
|
||||
val scratch32BitRegister = Register(D32, R8)
|
||||
|
||||
test("scratch 32-bit register toString") {
|
||||
assert(scratch32BitRegister.toString == "e8")
|
||||
assert(scratch32BitRegister.toString == "r8d")
|
||||
}
|
||||
|
||||
val memLocationWithHex = MemLocation(0x12345678)
|
||||
|
||||
test("mem location with hex toString") {
|
||||
assert(memLocationWithHex.toString == "[0x12345678]")
|
||||
}
|
||||
|
||||
val memLocationWithRegister = MemLocation(named64BitRegister)
|
||||
val memLocationWithRegister = MemLocation(named64BitRegister, Q64)
|
||||
|
||||
test("mem location with register toString") {
|
||||
assert(memLocationWithRegister.toString == "[rax]")
|
||||
assert(memLocationWithRegister.toString == "qword ptr [rax]")
|
||||
}
|
||||
|
||||
val immediateVal = ImmediateVal(123)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user