refactor: extract stack into seperate class
This commit is contained in:
Alex Ling
parent
8ed94e4df3
commit
3f76a2c5bf
@ -10,7 +10,6 @@ object asmGenerator {
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val RAX = Register(RegSize.R64, RegName.AX)
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val EAX = Register(RegSize.E32, RegName.AX)
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val RSP = Register(RegSize.R64, RegName.SP)
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val ESP = Register(RegSize.E32, RegName.SP)
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val EDX = Register(RegSize.E32, RegName.DX)
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val RDI = Register(RegSize.R64, RegName.DI)
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@ -37,14 +36,14 @@ object asmGenerator {
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}
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def generateAsm(microProg: Program): List[AsmLine] = {
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given stack: LinkedHashMap[Ident, Int] = LinkedHashMap[Ident, Int]()
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given stack: Stack = Stack()
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given strings: ListBuffer[String] = ListBuffer[String]()
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val Program(funcs, main) = microProg
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val progAsm =
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LabelDef("main") ::
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funcPrologue() ++
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alignStack() ++
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List(stack.align()) ++
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main.flatMap(generateStmt) ++
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List(Move(RAX, ImmediateVal(0))) ++
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funcEpilogue() ++
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@ -61,7 +60,7 @@ object asmGenerator {
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}
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def wrapFunc(labelName: String, funcBody: List[AsmLine])(using
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stack: LinkedHashMap[Ident, Int],
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stack: Stack,
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strings: ListBuffer[String]
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): List[AsmLine] = {
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LabelDef(labelName) ::
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@ -71,74 +70,71 @@ object asmGenerator {
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}
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def generateBuiltInFuncs()(using
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stack: LinkedHashMap[Ident, Int],
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stack: Stack,
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strings: ListBuffer[String]
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): List[AsmLine] = {
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wrapFunc(
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labelGenerator.getLabel(Builtin.Exit),
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alignStack() ++
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List(assemblyIR.Call(CLibFunc.Exit))
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List(stack.align(), assemblyIR.Call(CLibFunc.Exit))
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) ++
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wrapFunc(
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labelGenerator.getLabel(Builtin.Printf),
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alignStack() ++
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List(
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assemblyIR.Call(CLibFunc.PrintF),
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Move(RDI, ImmediateVal(0)),
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assemblyIR.Call(CLibFunc.Fflush)
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)
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List(
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stack.align(),
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assemblyIR.Call(CLibFunc.PrintF),
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Move(RDI, ImmediateVal(0)),
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assemblyIR.Call(CLibFunc.Fflush)
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)
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) ++
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wrapFunc(
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labelGenerator.getLabel(Builtin.Malloc),
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alignStack() ++
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List()
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List(
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stack.align(),
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)
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) ++
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wrapFunc(labelGenerator.getLabel(Builtin.Free), List()) ++
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wrapFunc(
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labelGenerator.getLabel(Builtin.Read),
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alignStack() ++
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List(
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Push(RSI),
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Load(RSI, MemLocation(RSP)),
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assemblyIR.Call(CLibFunc.Scanf),
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Pop(RAX)
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)
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List(
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stack.align(),
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stack.push(RSI),
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Load(RSI, stack.head),
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assemblyIR.Call(CLibFunc.Scanf),
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stack.pop(RAX)
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)
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)
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}
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def generateStmt(
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stmt: Stmt
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)(using stack: LinkedHashMap[Ident, Int], strings: ListBuffer[String]): List[AsmLine] =
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)(using stack: Stack, strings: ListBuffer[String]): List[AsmLine] =
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stmt match {
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case Assign(lhs, rhs) =>
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var dest: () => IndexAddress =
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() => IndexAddress(RSP, 0) // gets overrwitten
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() => IndexAddress(RAX, 0) // gets overrwitten
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(lhs match {
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case ident: Ident =>
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dest = stack.accessVar(ident)
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if (!stack.contains(ident)) {
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stack += (ident -> (stack.size + 1))
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dest = accessVar(ident)
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List(Subtract(RSP, ImmediateVal(8)))
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} else {
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dest = accessVar(ident)
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List()
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}
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List(stack.reserve(ident))
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} else Nil
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// TODO lhs = arrayElem
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case _ =>
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// dest = ???
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List()
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}) ++
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evalExprOntoStack(rhs) ++
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List(Pop(RAX),
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Move(dest(), RAX),
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List(
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stack.pop(RAX),
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Move(dest(), RAX),
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)
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case If(cond, thenBranch, elseBranch) => {
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val elseLabel = labelGenerator.getLabel()
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val endLabel = labelGenerator.getLabel()
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evalExprOntoStack(cond) ++
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List(
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Compare(MemLocation(RSP, SizeDir.Word), ImmediateVal(0)),
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Add(RSP, ImmediateVal(8)),
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Compare(stack.head(SizeDir.Word), ImmediateVal(0)),
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stack.drop(),
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Jump(LabelArg(elseLabel), Cond.Equal)
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) ++
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thenBranch.flatMap(generateStmt) ++
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@ -152,8 +148,8 @@ object asmGenerator {
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List(LabelDef(startLabel)) ++
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evalExprOntoStack(cond) ++
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List(
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Compare(MemLocation(RSP, SizeDir.Word), ImmediateVal(0)),
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Add(RSP, ImmediateVal(8)),
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Compare(stack.head(SizeDir.Word), ImmediateVal(0)),
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stack.drop(),
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Jump(LabelArg(endLabel), Cond.Equal)
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) ++
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body.flatMap(generateStmt) ++
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@ -161,21 +157,21 @@ object asmGenerator {
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}
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case microWacc.Return(expr) =>
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evalExprOntoStack(expr) ++
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List(Pop(RAX), assemblyIR.Return())
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List(stack.pop(RAX), assemblyIR.Return())
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case call: microWacc.Call => generateCall(call)
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}
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def evalExprOntoStack(expr: Expr)(using
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stack: LinkedHashMap[Ident, Int],
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stack: Stack,
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strings: ListBuffer[String]
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): List[AsmLine] = {
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expr match {
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case IntLiter(v) =>
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List(Push(ImmediateVal(v)))
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List(stack.push(ImmediateVal(v)))
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case CharLiter(v) =>
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List(Push(ImmediateVal(v.toInt)))
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List(stack.push(ImmediateVal(v.toInt)))
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case ident: Ident =>
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List(Push(accessVar(ident)()))
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List(stack.push(stack.accessVar(ident)()))
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case ArrayLiter(elems) =>
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expr.ty match {
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case KnownType.String =>
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@ -191,13 +187,13 @@ object asmGenerator {
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LabelArg(s".L.str${strings.size - 1}")
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)
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),
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Push(RAX)
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stack.push(RAX)
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)
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// TODO other array types
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case _ => List()
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}
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case BoolLiter(v) => List(Push(ImmediateVal(if (v) 1 else 0)))
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case NullLiter() => List(Push(ImmediateVal(0)))
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case BoolLiter(v) => List(stack.push(ImmediateVal(if (v) 1 else 0)))
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case NullLiter() => List(stack.push(ImmediateVal(0)))
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case ArrayElem(value, indices) => List()
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case UnaryOp(x, op) =>
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op match {
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@ -208,12 +204,12 @@ object asmGenerator {
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case UnaryOperator.Len => List()
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case UnaryOperator.Negate =>
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List(
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Negate(MemLocation(RSP, SizeDir.Word))
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Negate(stack.head(SizeDir.Word))
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)
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case UnaryOperator.Not =>
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evalExprOntoStack(x) ++
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List(
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Xor(MemLocation(RSP, SizeDir.Word), ImmediateVal(1))
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Xor(stack.head(SizeDir.Word), ImmediateVal(1))
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)
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}
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@ -223,46 +219,46 @@ object asmGenerator {
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evalExprOntoStack(x) ++
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evalExprOntoStack(y) ++
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List(
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Pop(RAX),
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Add(MemLocation(RSP, SizeDir.Word), EAX)
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stack.pop(RAX),
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Add(stack.head(SizeDir.Word), EAX)
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// TODO OVERFLOWING
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)
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case BinaryOperator.Sub =>
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evalExprOntoStack(x) ++
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evalExprOntoStack(y) ++
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List(
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Pop(RAX),
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Subtract(MemLocation(RSP, SizeDir.Word), EAX)
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stack.pop(RAX),
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Subtract(stack.head(SizeDir.Word), EAX)
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// TODO OVERFLOWING
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)
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case BinaryOperator.Mul =>
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evalExprOntoStack(x) ++
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evalExprOntoStack(y) ++
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List(
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Pop(RAX),
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Multiply(EAX, MemLocation(RSP, SizeDir.Word)),
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Add(RSP, ImmediateVal(8)),
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Push(RAX)
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stack.pop(RAX),
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Multiply(EAX, stack.head(SizeDir.Word)),
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stack.drop(),
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stack.push(RAX)
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// TODO OVERFLOWING
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)
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case BinaryOperator.Div =>
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evalExprOntoStack(y) ++
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evalExprOntoStack(x) ++
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List(
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Pop(RAX),
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Divide(MemLocation(RSP, SizeDir.Word)),
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Add(RSP, ImmediateVal(8)),
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Push(RAX)
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stack.pop(RAX),
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Divide(stack.head(SizeDir.Word)),
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stack.drop(),
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stack.push(RAX)
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// TODO CHECK DIVISOR IS NOT 0
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)
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case BinaryOperator.Mod =>
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evalExprOntoStack(y) ++
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evalExprOntoStack(x) ++
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List(
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Pop(RAX),
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Divide(MemLocation(RSP, SizeDir.Word)),
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Add(RSP, ImmediateVal(8)),
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Push(RDX)
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stack.pop(RAX),
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Divide(stack.head(SizeDir.Word)),
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stack.drop(),
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stack.push(RDX)
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// TODO CHECK DIVISOR IS NOT 0
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)
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case BinaryOperator.Eq =>
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@ -281,15 +277,15 @@ object asmGenerator {
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evalExprOntoStack(x) ++
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evalExprOntoStack(y) ++
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List(
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Pop(RAX),
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And(MemLocation(RSP, SizeDir.Word), EAX)
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stack.pop(RAX),
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And(stack.head(SizeDir.Word), EAX)
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)
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case BinaryOperator.Or =>
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evalExprOntoStack(x) ++
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evalExprOntoStack(y) ++
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List(
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Pop(RAX),
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Or(MemLocation(RSP, SizeDir.Word), EAX)
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stack.pop(RAX),
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Or(stack.head(SizeDir.Word), EAX)
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)
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}
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case call: microWacc.Call => generateCall(call)
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@ -297,24 +293,24 @@ object asmGenerator {
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}
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def generateCall(call: microWacc.Call)(using
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stack: LinkedHashMap[Ident, Int],
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stack: Stack,
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strings: ListBuffer[String]
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): List[AsmLine] = {
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val argRegs = List(RDI, RSI, RDX, RCX, R8, R9)
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val microWacc.Call(target, args) = call
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argRegs.zip(args).flatMap { (reg, expr) =>
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evalExprOntoStack(expr) ++
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List(Pop(reg))
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List(stack.pop(reg))
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} ++
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args.drop(argRegs.size).flatMap(evalExprOntoStack) ++
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List(assemblyIR.Call(LabelArg(labelGenerator.getLabel(target)))) ++
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(if (args.size > argRegs.size) {
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List(Load(RSP, IndexAddress(RSP, (args.size - argRegs.size) * 8)))
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List(stack.reserve(args.size - argRegs.size))
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} else Nil)
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}
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// def readIntoVar(dest: IndexAddress, readType: Builtin.ReadInt.type | Builtin.ReadChar.type)(using
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// stack: LinkedHashMap[Ident, Int],
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// stack: Stack,
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// strings: ListBuffer[String]
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// ): List[AsmLine] = {
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// readType match {
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@ -339,41 +335,33 @@ object asmGenerator {
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// }
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def generateComparison(x: Expr, y: Expr, cond: Cond)(using
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stack: LinkedHashMap[Ident, Int],
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stack: Stack,
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strings: ListBuffer[String]
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): List[AsmLine] = {
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evalExprOntoStack(x) ++
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evalExprOntoStack(y) ++
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List(
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Pop(RAX),
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Compare(MemLocation(RSP, SizeDir.Word), EAX),
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stack.pop(RAX),
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Compare(stack.head(SizeDir.Word), EAX),
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Set(Register(RegSize.Byte, RegName.AL), cond),
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And(EAX, ImmediateVal(_8_BIT_MASK)),
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Load(RSP, IndexAddress(RSP, 8)),
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Push(RAX)
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And(RAX, ImmediateVal(_8_BIT_MASK)),
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stack.drop(),
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stack.push(RAX)
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)
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}
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def accessVar(ident: Ident)(using stack: LinkedHashMap[Ident, Int]): () => IndexAddress =
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() => IndexAddress(RSP, (stack.size - stack(ident)) * 8)
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def alignStack()(using stack: LinkedHashMap[Ident, Int]): List[AsmLine] = {
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List(
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And(RSP, ImmediateVal(-16))
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)
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}
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// Missing a sub instruction but dont think we need it
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def funcPrologue(): List[AsmLine] = {
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def funcPrologue()(using stack: Stack): List[AsmLine] = {
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List(
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Push(RBP),
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Move(RBP, RSP)
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stack.push(RBP),
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Move(RBP, Register(RegSize.R64, RegName.SP))
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)
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}
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def funcEpilogue(): List[AsmLine] = {
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def funcEpilogue()(using stack: Stack): List[AsmLine] = {
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List(
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Move(RSP, RBP),
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Pop(RBP),
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Move(Register(RegSize.R64, RegName.SP), RBP),
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stack.pop(RBP),
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assemblyIR.Return()
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)
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}
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@ -383,7 +371,7 @@ object asmGenerator {
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// TODO: refactor, really ugly function
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// def printF(expr: Expr)(using
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// stack: LinkedHashMap[Ident, Int],
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// stack: Stack,
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// strings: ListBuffer[String]
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// ): List[AsmLine] = {
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// // determine the format string
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@ -442,7 +430,7 @@ object asmGenerator {
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// prints a new line
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// def printLn()(using
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// stack: LinkedHashMap[Ident, Int],
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// stack: Stack,
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// strings: ListBuffer[String]
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// ): List[AsmLine] = {
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// strings += ""
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@ -461,4 +449,44 @@ object asmGenerator {
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// )
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// }
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class Stack {
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private val stack = LinkedHashMap[Expr | Int, Int]()
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private val RSP = Register(RegSize.R64, RegName.SP)
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def next: Int = stack.size + 1
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def push(expr: Expr, src: Src): AsmLine = {
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stack += expr -> next
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Push(src)
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}
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def push(src: Src): AsmLine = {
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stack += stack.size -> next
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Push(src)
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}
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def pop(dest: Src): AsmLine = {
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stack.remove(stack.last._1)
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Pop(dest)
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}
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def reserve(ident: Ident): AsmLine = {
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stack += ident -> next
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Subtract(RSP, ImmediateVal(8))
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}
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def reserve(n: Int = 1): AsmLine = {
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(1 to n).foreach(_ => stack += stack.size -> next)
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Subtract(RSP, ImmediateVal(n*8))
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}
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def drop(n : Int = 1): AsmLine = {
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(1 to n).foreach(_ => stack.remove(stack.last._1))
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Add(RSP, ImmediateVal(n*8))
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}
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def accessVar(ident: Ident): () => IndexAddress = () => {
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IndexAddress(RSP, (stack.size - stack(ident)) * 8)
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}
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def head: MemLocation = MemLocation(RSP)
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def head(size: SizeDir): MemLocation = MemLocation(RSP, size)
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def contains(ident: Ident): Boolean = stack.contains(ident)
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// TODO: Might want to actually properly handle this with the LinkedHashMap too
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def align(): AsmLine = And(RSP, ImmediateVal(-16))
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}
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}
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