93 lines
5.5 KiB
HTML
93 lines
5.5 KiB
HTML
<HTML>
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<HEAD>
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<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
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<META NAME="Author" CONTENT="Joshua Neal">
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<META NAME="Description" CONTENT="Pure VGA/SVGA hardware programming (registers, identification, and otherlow-level stuff.)">
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<META NAME="KeyWords" CONTENT="VGA SVGA hardware video programming">
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<TITLE>FreeVGA - Overview of Video Hardware Functionality</TITLE>
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</HEAD>
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<BODY>
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<CENTER><A HREF="home.htm">Home</A> <A HREF="#intro">Introduction</A> <A HREF="#frame">Frame
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Buffer</A> <A HREF="#graphics">Graphics Controller</A> <A HREF="#display generation">Display
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Generation</A> <A HREF="home.htm#background">Back</A>
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<HR><B>Hardware Level VGA and SVGA Video Programming Information Page</B></CENTER>
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<CENTER>Overview of Video Hardware Functionality
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<HR></CENTER>
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<A NAME="intro"></A><B>Introduction</B>
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<BR> This page contains a general
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overview of the functionality of VGA and SVGA cards into various sections,
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and gives a description of the functions of each section. This is
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intended to be a general description for those unfamiliar to the functionality
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and capabilities of graphics hardware. The basic function of graphics
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hardware is to allow the CPU to manipulate memory specific to the graphics
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hardware, and to take the information stored in that memory and output
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it in a form that a monitor or LCD panel can use.
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<P><A NAME="frame"></A><B>Frame Buffer</B>
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<BR> This is the component of
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the video hardware that stores the pixels and information to be displayed
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on the monitor. This is the center of the video hardware, as nearly
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all operations are performed on or using this data. The frame buffer
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is a form of RAM, which is typically located outside the main graphics
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chip and are implemented using DRAM chips; however, more sophisticated
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forms of RAM that are ideal for video hardware applications, such as VRAM.
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The amount of video memory that is present determines the maximum resolution
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that the hardware can generate. The frame buffer is usually mapped
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into a region of the host CPU's address space allowing it to be accessed
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as if it were a portion of the main memory. For example, in the VGA,
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this memory is mapped into the lower 1M of the CPU address space, allowing
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it to be directly accessable to real mode applications, which cannot directly
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access the remaining memory. In the VGA, this memory is broken up
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into 4 separate color planes, which are recombined to produce the actual
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pixel values at the time of display generation.
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<P><A NAME="graphics"></A><B>Graphics Controller</B>
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<BR> This is the video chipset's
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host interface to the frame buffer, and is part of the main graphics chip
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or chips. It allows the host CPU to manipulate the frame buffer in
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a fashion suited to the task of graphics operations. It allows certain
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methods of access that are designed to reduced the CPU requirements for
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performing standard video operations, particularly in accelerated chipsets,
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which can have a quite complicated set of access methods which can include
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line drawing, area and pattern fill, color conversion/expansion, and even
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3d rendering acceleration. For example, in the VGA the graphics controller
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allows one write by the CPU to its mapped memory region below 1M to affect
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all four color planes, as well as allowing faster transfers of video data
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from one region to another in video memory.
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<P><A NAME="display generation"></A><B>Display Generation</B>
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<BR> This portion of the graphics
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hardware is involved in taking the data in the frame buffer, converting
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the pixel or character information stored by the graphics controller, and
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converting it into the analog signals required by the monitor or lcd display.
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The pixel data is first sequenced, or read serially from the frame buffer,
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then converted into analog color information, either by a palette look-up
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table, or by directly converting into red, green, and blue components.
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The CRT controller at the same time adds timing signals that allow the
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monitor to display the analog color information on the display. For
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example, in the VGA these components are made up of the sequencer, attribute
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controller, CRT controller, DAC, and palette table. The sequencer
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reads the information from the frame buffer, and converts it into pixel
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color information, as well as sends signals to the CRT controller such
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that it can provide the timing signals the monitor requires. This
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color information is formatted by the attribute controller in such a way
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that the pixel values can be submitted to the DAC. The DAC then looks
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up these values in its palette table which contains red, green, and blue
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intensities for each of the colors that the attribute controller generates,
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then converts it into an analog signal that is output to the VGA connector
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along with the timing signals generated by the CRT controller. If
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the display is an LCD panel such as found in laptops, the DAC and associated
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support hardware convert the pixel values to signals that the LCD panel
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displays directly.
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<P>Notice: All trademarks used or referred to on this page are the property
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of their respective owners.
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<BR>All pages are Copyright © 1997, 1998, J. D. Neal, except where
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noted. Permission for utilization and distribution is subject to the terms
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of the <A HREF="license.htm">FreeVGA Project Copyright License</A>.
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<BR>
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</BODY>
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</HTML>
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