211 lines
14 KiB
HTML
211 lines
14 KiB
HTML
<HTML>
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<HEAD>
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<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
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<META NAME="Author" CONTENT="Joshua Neal">
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<META NAME="Description" CONTENT="Pure VGA/SVGA hardware programming (registers, identification, and otherlow-level stuff.)">
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<META NAME="KeyWords" CONTENT="VGA SVGA hardware video programming">
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<TITLE>FreeVGA - VGA Display Generation</TITLE>
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</HEAD>
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<BODY>
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<CENTER><A HREF="../home.htm">Home</A> <A HREF="#intro">Intro</A> <A HREF="#clocks">Clocks</A>
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<A HREF="#horiz">Horizontal</A> <A HREF="#vert">Vertical</A> <A HREF="#monitor">Monitoring</A>
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<A HREF="#misc">Misc</A> <A HREF="vga.htm#general">Back</A>
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<HR><B>Hardware Level VGA and SVGA Video Programming Information Page</B></CENTER>
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<CENTER>VGA Display Generation
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<HR></CENTER>
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<A NAME="intro"></A><B>Introduction</B>
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<BR> This page documents the
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configuration of the VGA's CRTC registers which control the framing and
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timing of video signals sent to the display device, usually a monitor.
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<P><A NAME="clocks"></A><B>Dot Clocks</B>
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<BR> The standard VGA has two
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"standard" dot clock frequencies available to it, as well as a possible
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"external" clock source, which is implementation dependent. The two
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standard clock frequencies are nominally 25 Mhz and 28 MHz. Some
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chipsets use 25.000 MHz and 28.000 MHz, while others use slightly greater
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clock frequencies. The IBM VGA chipset I have uses 25.1750 MHz
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Mhz and 28.3220 crystals. Some newer cards use the closest generated
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frequency produced by their clock chip. In most circumstances the
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IBM VGA timings can be assumed as the monitor should allow an amount of
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variance; however, if you know the actual frequencies used you should use
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them in your timing calculations.
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<BR> The dot clock source in
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the VGA hardware is selected using the <A HREF="extreg.htm#3CCR3C2W">Clock
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Select</A> field. For the VGA, two of the values are undefined; some
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SVGA chipsets use the undefined values for clock frequencies used for 132
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column mode and such. The 25 MHz clock is designed for 320 and 640
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pixel modes and the 28 MHz is designed for 360 and 720 pixel modes. The
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<A HREF="seqreg.htm#01">Dot Clock Rate</A> field specifies whether to use
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the dot clock source directly or to divide it in half before using it as
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the actual dot clock rate.
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<P><A NAME="horiz"></A><B>Horizontal Timing</B>
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<BR> The VGA measures horizontal
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timing periods in terms of character clocks, which can either be 8 or 9
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dot clocks, as specified by the <A HREF="seqreg.htm#01">9/8 Dot Mode</A>
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field. The 9 dot clock mode was included for monochrome emulation
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and 9-dot wide character modes, and can be used to provide 360 and 720
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pixel wide modes that work on all standard VGA monitors, when combined
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with a 28 Mhz dot clock. The VGA uses a horizontal character counter which
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is incremented at each character, which the horizontal timing circuitry
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compares against the values of the horizontal timing fields to control
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the horizontal state. The horizontal periods that are controlled are the
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active display, overscan, blanking, and refresh periods.
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<BR> The start of the active
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display period coincides with the resetting of the horizontal character
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counter, thus is fixed at zero. The value at which the horizontal
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character is reset is controlled by the <A HREF="crtcreg.htm#00">Horizontal
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Total</A> field. Note, however, that the value programmed into the <A HREF="crtcreg.htm#00">Horizontal
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Total</A> field is actually 5 less than the actual value due to timing
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concerns.
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<BR> The end of the active display
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period is controlled by the <A HREF="crtcreg.htm#01">End Horizontal Display</A>
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field. When the horizontal character counter is equal to the value
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of this field, the sequencer begins outputting the color specified by the
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<A HREF="attrreg.htm#11">Overscan Palette Index</A> field. This continues
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until the active display begins at the beginning of the next scan line
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when the active display begins again. Note that the horizontal blanking
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takes precedence over the sequencer and attribute controller.
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<BR> The horizontal blanking
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period begins when the character clock equals the value of the <A HREF="crtcreg.htm#02">Start
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Horizontal Blanking</A> field. During the horizontal blanking period,
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the output voltages of the DAC signal the monitor to turn off the guns.
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Under normal conditions, this prevents the overscan color from being displayed
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during the horizontal retrace period. This period extends until the
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lower 6 bits of the <A HREF="crtcreg.htm#03">End Horizontal Blanking</A>
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field match the lower 6 bits of the horizontal character counter.
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This allows for a blanking period from 1 to 64 character clocks, although
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some implementations may treat 64 as 0 character clocks in length.
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The blanking period may occur anywhere in the scan line, active display
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or otherwise even though its meant to appear outside the active display
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period. It takes precedence over all other VGA output. There
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is also no requirement that blanking occur at all. If the <A HREF="crtcreg.htm#02">Start
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Horizontal Blanking</A> field falls outside the maximum value of the character
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clock determined by the <A HREF="crtcreg.htm#00">Horizontal Total</A> field,
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then no blanking will occur at all. Note that due to the setting
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of the <A HREF="crtcreg.htm#00">Horizontal Total</A> field, the first match
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for the <A HREF="crtcreg.htm#03">End Horizontal Blanking</A> field may
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be on the following scan line.
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<BR> Similar to the horizontal
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blanking period, the horizontal retrace period is specified by the <A HREF="crtcreg.htm#04">Start
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Horizontal Retrace</A> and <A HREF="crtcreg.htm#05">End Horizontal Retrace</A>
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fields. The horizontal retrace period begins when the character clock equals
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the value stored in the <A HREF="crtcreg.htm#04">Start Horizontal Retrace</A>
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field. The horizontal retrace ends when the lower 5 bits of the character
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clock match the bit pattern stored in the <A HREF="crtcreg.htm#05">End
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Horizontal Retrace</A> field, allowing a retrace period from 1 to 32 clocks;
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however, a particular implementation may treat 32 clocks as zero clocks
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in length. The operation of this is identical to that of the horizontal
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blanking mechanism with the exception of being a 5 bit comparison instead
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of 6, and affecting the horizontal retrace signal instead of the horizontal
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blanking.
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<BR> There are two horizontal
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timing fields that are described as being related to internal timings of
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the VGA, the <A HREF="crtcreg.htm#03">Display Enable Skew</A> and <A HREF="crtcreg.htm#05">Horizontal
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Retrace Skew</A> fields. In the VGA they do seem to affect the timing,
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but also do not seem to be necessary for the operation of the VGA and are
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pretty much unused. These registers were required by the IBM VGA
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implementations, so I'm assuming this was added in the early stages of
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the VGA design for EGA compatibility, but the internal timings were changed
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to more friendly ones making the use of these fields unnecessary.
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It seems to be totally safe to set these fields to 0 and ignore them.
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See the register descriptions for more details, if you have to deal with
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software that programs them.
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<P><A NAME="vert"></A><B>Vertical Timing</B>
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<BR> The VGA maintains a scanline
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counter which is used to measure vertical timing periods. This counter
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begins at zero which coincides with the first scan line of the active display.
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This counter is set to zero before the beginning of the first scanline
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of the active display. Depending on the setting of the <A HREF="crtcreg.htm#17">Divide
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Scan Line Clock by 2</A> field, this counter is incremented either every
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scanline, or every second scanline. The vertical scanline counter
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is incremented before the beginning of each horizontal scan line, as all
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of the VGA's vertical timing values are measured at the beginning of the
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scan line, after the counter has ben set/incremented. The maximum
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value of the scanline counter is specified by the <A HREF="crtcreg.htm#06">Vertical
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Total</A> field. Note that, like the rest of the vertical timing
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values that "overflow" an 8-bit register, the most significant bits are
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located in the <A HREF="crtcreg.htm#07">Overflow Register</A>. The
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<A HREF="crtcreg.htm#06">Vertical Total</A> field is programmed with the
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value of the scanline counter at the beginning of the last scanline.
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<BR> The vertical active display
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period begins when the scanline counter is at zero, and extends up to the
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value specified by the <A HREF="crtcreg.htm#12">Vertical Display End</A>
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field. This field is set with the value of the scanline counter at
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the beginning of the first inactive scanline, telling the video hardware
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when to stop outputting scanlines of sequenced pixel data and outputs the
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attribute specified by the <A HREF="attrreg.htm#11">Overscan Palette Index</A>
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field in the horizontal active display period of those scanlines.
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This continues until the start of the next frame when the active display
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begins again.
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<BR> The <A HREF="crtcreg.htm#15">Start
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Vertical Blanking</A> and <A HREF="crtcreg.htm#16">End Vertical Blanking</A>
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fields control the vertical blanking interval. The <A HREF="crtcreg.htm#15">Start
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Vertical Blanking</A> field is programmed with the value of the scanline
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counter at the beginning of the scanline to begin blanking at. The
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value of the <A HREF="crtcreg.htm#16">End Vertical Blanking</A> field is
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set to the lower eight bits of the scanline counter at the beginning of
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the scanline after the last scanline of vertical blanking.
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<BR> The <A HREF="crtcreg.htm#10">Vertical
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Retrace Start</A> and <A HREF="crtcreg.htm#11">Vertical Retrace End</A>
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fields determine the length of the vertical retrace interval. The
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<A HREF="crtcreg.htm#10">Vertical Retrace Start</A> field contains the
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value of the scanline counter at the beginning of the first scanline where
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the vertical retrace signal is asserted. The <A HREF="crtcreg.htm#11">Vertical
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Retrace End</A> field is programmed with the value of the lower four bits
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of the scanline counter at the beginning of the scanline after the last
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scanline where the vertical retrace signal is asserted.
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<P><A NAME="monitor"></A><B>Monitoring Timing</B>
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<BR> There are certain operations
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that should be performed during certain periods of the display cycle to
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minimize visual artifacts, such as attribute and DAC writes. There
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are two bit fields that return the current state of the VGA, the <A HREF="extreg.htm#3xAR">Display
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Disabled</A> and <A HREF="extreg.htm#3xAR">Vertical Retrace</A> fields.
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The <A HREF="extreg.htm#3xAR">Display Disabled</A> field is set to 1 when
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the display enable signal is not asserted, providing the programmer with
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a means to determine if the video hardware is currently refreshing the
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active display or it is currently outputting blanking.
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<BR> The <A HREF="extreg.htm#3xAR">Vertical
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Retrace</A> field signals whether or not the VGA is in a vertical retrace
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period. This is useful for determining the end of a display period,
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which can be used by applications that need to update the display every
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period such as when doing animation. Under normal conditions, when
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the blanking signal is asserted during the entire vertical retrace, this
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can also be used to detect this period of blanking, such that a large amount
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of register accesses can be performed, such as reloading the complete set
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of DAC entries.
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<P><A NAME="misc"></A><B>Miscellaneous</B>
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<BR> There are a few registers
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that affect display generation, but don't fit neatly into the horizontal
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or vertical timing categories. The first is the <A HREF="crtcreg.htm#17">Sync
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Enable</A> field which controls whether the horizontal and vertical sync
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signals are sent to the display or masked off. The sync signals should
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be disabled while setting up a new mode to ensure that an improper signal
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that could damage the display is not being output. Keeping the sync
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disabled for a period of one or more frames helps the display determine
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that a mode change has occurred as well.
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<BR> The <A HREF="crtcreg.htm#11">Memory Refresh Bandwidth</A>
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field is used by the original IBM VGA hardware and some compatible VGA/SVGA
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chipsets to control how often the display memory is refreshed. This
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field controls whether the VGA hardware provides 3 or 5 memory refresh
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cycles per scanline. At or above VGA horizontal refresh rates, this
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field should be programmed for 3 memory refresh cycles per scanline.
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Below this rate, for compatibility's sake the 5 memory refresh cycles per
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scanline setting might be safer, see the <A HREF="crtcreg.htm#11">Memory
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Refresh Bandwidth</A> field for (slightly) more information.
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<P>
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<BR>Notice: All trademarks used or referred to on this page are the property
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of their respective owners.
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<BR>All pages are Copyright © 1997, 1998, J. D. Neal, except where
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noted. Permission for utilization and distribution is subject to the terms
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of the <A HREF="license.htm">FreeVGA Project Copyright License</A>.
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</BODY>
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</HTML>
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