1356 lines
40 KiB
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1356 lines
40 KiB
HTML
<HTML>
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<HEAD>
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<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
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<META NAME="Author" CONTENT="Joshua Neal">
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<META NAME="Description" CONTENT="Pure VGA/SVGA hardware programming (registers, identification, and other low-level stuff.)">
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<META NAME="KeyWords" CONTENT="VGA SVGA hardware video programming">
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<TITLE>VGA/SVGA Video Programming--CRT Controller Registers</TITLE>
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</HEAD>
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<BODY>
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<CENTER><A HREF="../home.htm">Home</A> <A HREF="vga.htm#register">Back</A>
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<HR WIDTH="100%"><B>Hardware Level VGA and SVGA Video Programming Information
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Page</B></CENTER>
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<CENTER>CRT Controller Registers
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<HR WIDTH="100%"></CENTER>
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<P> The CRT Controller (CRTC)
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Registers are accessed via a pair of registers, the CRTC Address Register
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and the CRTC Data Register. See the <A HREF="vgareg.htm">Accessing the
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VGA Registers</A> section for more details. The Address Register is located
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at port 3x4h and the Data Register is located at port 3x5h. The value
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of the x in 3x4h and 3x5h is dependent on the state of the <A HREF="extreg.htm#3CCR3C2W">Input/Output
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Address Select</A> field, which allows these registers to be mapped at
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3B4h-3B5h or 3D4h-3D5h. Note that when the <A HREF="#11">CRTC
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Registers Protect Enable</A> field is set to 1, writing to register indexes
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00h-07h is prevented, with the exception of the <A HREF="#07">Line Compare</A>
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field of the <A HREF="#07">Overflow Register</A>.
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<UL>
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<LI>
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Index 00h -- <A HREF="#00">Horizontal Total Register</A></LI>
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<LI>
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Index 01h -- <A HREF="#01">End Horizontal Display Register</A></LI>
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<LI>
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Index 02h -- <A HREF="#02">Start Horizontal Blanking Register</A></LI>
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<LI>
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Index 03h -- <A HREF="#03">End Horizontal Blanking Register</A></LI>
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<LI>
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Index 04h -- <A HREF="#04">Start Horizontal Retrace Register</A></LI>
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<LI>
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Index 05h -- <A HREF="#05">End Horizontal Retrace Register</A></LI>
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<LI>
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Index 06h -- <A HREF="#06">Vertical Total Register</A></LI>
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<LI>
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Index 07h -- <A HREF="#07">Overflow Register</A></LI>
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<LI>
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Index 08h -- <A HREF="#08">Preset Row Scan Register</A></LI>
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<LI>
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Index 09h -- <I><A HREF="#09">Maximum Scan Line Register</A></I></LI>
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<LI>
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Index 0Ah -- <A HREF="#0A">Cursor Start Register</A></LI>
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<LI>
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Index 0Bh -- <A HREF="#0B">Cursor End Register</A></LI>
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<LI>
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Index 0Ch -- <A HREF="#0C">Start Address High Register</A></LI>
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<LI>
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Index 0Dh -- <A HREF="#0D">Start Address Low Register</A></LI>
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<LI>
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Index 0Eh -- <A HREF="#0E">Cursor Location High Register</A></LI>
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<LI>
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Index 0Fh -- <A HREF="#0F">Cursor Location Low Register</A></LI>
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<LI>
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Index 10h -- <A HREF="#10">Vertical Retrace Start Register</A></LI>
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<LI>
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Index 11h -- <A HREF="#11">Vertical Retrace End Register</A></LI>
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<LI>
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Index 12h -- <A HREF="#12">Vertical Display End Register</A></LI>
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<LI>
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Index 13h -- <A HREF="#13">Offset Register</A></LI>
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<LI>
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Index 14h -- <I><A HREF="#14">Underline Location Register</A></I></LI>
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<LI>
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Index 15h -- <A HREF="#15">Start Vertical Blanking Register</A></LI>
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<LI>
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Index 16h -- <A HREF="#16">End Vertical Blanking</A></LI>
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<LI>
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Index 17h -- <I><A HREF="#17">CRTC Mode Control Register</A></I></LI>
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<LI>
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Index 18h -- <A HREF="#18">Line Compare Register</A></LI>
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</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="00"></A><B>Horizontal Total Register (Index
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00h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD COLSPAN="8" WIDTH="600">Horizontal Total</TD>
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</TR>
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</TABLE>
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<UL>
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<LI>
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<B>Horizontal Total</B></LI>
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<BR>This field is used to specify the number of character clocks per scan
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line. This field, along with the dot rate selected, controls the
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horizontal refresh rate of the VGA by specifying the amount of time one
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scan line takes. This field is not programmed with the actual number
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of character clocks, however. Due to timing factors of the VGA hardware
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(which, for compatibility purposes has been emulated by VGA compatible
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chipsets), the actual horizontal total is 5 character clocks more than
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the value stored in this field, thus one needs to subtract 5 from the actual
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horizontal total value desired before programming it into this register.</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="01"></A><B>End Horizontal Display Register
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(Index 01h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD COLSPAN="8" WIDTH="600">End Horizontal Display</TD>
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</TR>
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</TABLE>
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<UL>
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<LI>
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<B>End Horizontal Display</B></LI>
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<BR>This field is used to control the point that the sequencer stops outputting
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pixel values from display memory, and sequences the pixel value specified
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by the <A HREF="attrreg.htm#11">Overscan Palette Index</A> field for the
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remainder of the scan line. The overscan begins the character clock
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after the the value programmed into this field. This register should
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be programmed with the number of character clocks in the active display
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- 1. Note that the active display may be affected by the <A HREF="#03">Display
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Enable Skew</A> field.
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<BR> </UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="02"></A><B>Start Horizontal Blanking Register
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(Index 02h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD COLSPAN="8" WIDTH="600">Start Horizontal Blanking</TD>
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</TR>
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</TABLE>
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<UL>
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<LI>
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<B>Start Horizontal Blanking</B></LI>
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<BR>This field is used to specify the character clock at which the horizontal
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blanking period begins. During the horizontal blanking period, the
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VGA hardware forces the DAC into a blanking state, where all of the intensities
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output are at minimum value, no matter what color information the attribute
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controller is sending to the DAC. This field works in conjunction
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with the <A HREF="#03">End Horizontal Blanking</A> field to specify the
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horizontal blanking period. Note that the horizontal blanking can
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be programmed to appear anywhere within the scan line, as well as being
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programmed to a value greater than the <A HREF="crtcreg.htm#00">Horizontal
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Total</A> field preventing the horizontal blanking from occurring at all.</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="03"></A><B>End Horizontal Blanking Register
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(Index 03h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">EVRA</TD>
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<TD COLSPAN="2" WIDTH="150">Display Enable Skew</TD>
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<TD COLSPAN="5" WIDTH="375">End Horizontal Blanking</TD>
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</TR>
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</TABLE>
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<UL>
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<LI>
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<B>EVRA -- Enable Vertical Retrace Access</B></LI>
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<BR>This field was used in the IBM EGA to provide access to the light pen
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input values as the light pen registers were mapped over CRTC indexes 10h-11h.
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The VGA lacks capability for light pen input, thus this field is normally
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forced to 1 (although always writing it as 1 might be a good idea for compatibility)
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, which in the EGA would enable access to the vertical retrace fields instead
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of the light pen fields.
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<LI>
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<B>Display Enable Skew</B></LI>
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<BR>This field affects the timings of the display enable circuitry in the
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VGA. The value of this field is the number of character clocks that the
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display enable "signal" is delayed. In all the VGA/SVGA chipsets
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I've tested, including a PS/2 VGA this field is always programmed to 0.
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Programming it to non-zero values results in the overscan being displayed
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over the number of characters programmed into this field at the beginning
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of the scan line, as well as the end of the active display being shifted
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the number of characters programmed into this field. The characters
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that extend past the normal end of the active display can be garbled in
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certain circumstances that is dependent on the particular VGA implementation.
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According to documentation from IBM, "<I>This skew control is needed to
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provide sufficient time for the CRT controller to read a character and
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attribute code from the video buffer, to gain access to the character generator,
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and go through the Horizontal PEL Panning register in the attribute controller.
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Each access requires the 'display enable' signal to be skewed one character
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clock so that the video output is synchronized with the horizontal and
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vertical retrace signals.</I>" as well as "<I>Note: Character skew is not
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adjustable on the Type 2 video and the bits are ignored; however, programs
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should set these bits for the appropriate skew to maintain compatibility.</I>"
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This may be required for some early IBM VGA implementations or may be simply
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an unused "feature" carried over along with its register description from
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the IBM EGA implementations that require the use of this field.
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<LI>
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<B>End Horizontal Blanking</B></LI>
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<BR>This contains bits 4-0 of the End Horizontal Blanking field which specifies
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the end of the horizontal blanking period. Bit 5 is located After
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the period has begun as specified by the <A HREF="#02">Start Horizontal
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Blanking</A> field, the 6-bit value of this field is compared against the
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lower 6 bits of the character clock. When a match occurs, the horizontal
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blanking signal is disabled. This provides from 1 to 64 character
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clocks although some implementations may match in the character clock specified
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by the <A HREF="#02">Start Horizontal Blanking</A> field, in which case
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the range is 0 to 63. Note that if blanking extends past the end
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of the scan line, it will end on the first match of this field on the next
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scan line.</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="04"></A><B>Start Horizontal Retrace Register
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(Index 04h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD COLSPAN="8" WIDTH="600">Start Horizontal Retrace</TD>
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</TR>
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</TABLE>
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<UL>
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<LI>
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<B>Start Horizontal Retrace</B></LI>
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<BR>This field specifies the character clock at which the VGA begins sending
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the horizontal synchronization pulse to the display which signals the monitor
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to retrace back to the left side of the screen. The end of this pulse
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is controlled by the <A HREF="#05">End Horizontal Retrace</A> field.
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This pulse may appear anywhere in the scan line, as well as set to a position
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beyond the <A HREF="crtcreg.htm#00">Horizontal Total</A> field which effectively
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disables the horizontal synchronization pulse.</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="05"></A><B>End Horizontal Retrace Register
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(Index 05h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">EHB5</TD>
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<TD COLSPAN="2" WIDTH="150">Horiz. Retrace Skew</TD>
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<TD COLSPAN="5" WIDTH="375">End Horizontal Retrace</TD>
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</TR>
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</TABLE>
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<UL>
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<LI>
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<B>EHB5 -- End Horizontal Blanking (bit 5)</B></LI>
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<BR>This contains bit 5 of the End Horizontal Blanking field. See
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the <A HREF="#03">End Horizontal Blanking Register</A> for details.
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<LI>
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<B>Horiz. Retrace Skew -- Horizontal Retrace Skew</B></LI>
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<BR>This field delays the start of the horizontal retrace period by the
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number of character clocks equal to the value of this field. From
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observation, this field is programmed to 0, with the exception of the 40
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column text modes where this field is set to 1. The VGA hardware
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simply acts as if this value is added to the <A HREF="#04">Start Horizontal
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Retrace</A> field. According to IBM documentation, "<I>For certain
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modes, the 'horizontal retrace' signal takes up the entire blanking interval.
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Some internal timings are generated by the falling edge of the 'horizontal
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retrace' signal. To ensure that the signals are latched properly, the 'retrace'
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signal is started before the end of the 'display enable' signal and then
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skewed several character clock times to provide the proper screen centering.</I>"
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This does not appear to be the case, leading me to believe this is yet
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another holdout from the IBM EGA implementations that do require the use
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of this field.
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<LI>
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<B>End Horizontal Retrace</B></LI>
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<BR>This field specifies the end of the horizontal retrace period, which
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begins at the character clock specified in the <A HREF="#04">Start Horizontal
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Retrace</A> field. The horizontal retrace signal is enabled until
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the lower 5 bits of the character counter match the 5 bits of this field.
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This provides for a horizontal retrace period from 1 to 32 character clocks.
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Note that some implementations may match immediately instead of 32 clocks
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away, making the effective range 0 to 31 character clocks.</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="06"></A><B>Vertical Total Register (Index 06h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD COLSPAN="8" WIDTH="600">Vertical Total</TD>
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</TR>
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</TABLE>
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<UL><B>Vertical Total</B>
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<BR>This contains the lower 8 bits of the Vertical Total field. Bits
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9-8 of this field are located in the <A HREF="#07">Overflow Register</A>.
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This field determines the number of scanlines in the active display and
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thus the length of each vertical retrace. This field contains the
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value of the scanline counter at the beginning of the last scanline in
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the vertical period.</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="07"></A><B>Overflow Register (Index 07h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">VRS9</TD>
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<TD WIDTH="75">VDE9</TD>
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<TD WIDTH="75">VT9</TD>
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<TD WIDTH="75">LC8</TD>
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<TD WIDTH="75">SVB8</TD>
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<TD WIDTH="75">VRS8</TD>
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<TD WIDTH="75">VDE8</TD>
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<TD WIDTH="75">VT8</TD>
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</TR>
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</TABLE>
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<UL>
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<LI>
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<B>VRS9 -- Vertical Retrace Start (bit 9)</B></LI>
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<BR>Specifies bit 9 of the Vertical Retrace Start field. See the
|
|
<A HREF="#10">Vertical Retrace Start Register</A> for details.
|
|
<LI>
|
|
<B>VDE9 -- Vertical Display End (bit9)</B></LI>
|
|
|
|
<BR>Specifies bit 9 of the Vertical Display End field. See the <A HREF="#12">Vertical
|
|
Display End Register</A> for details.
|
|
<LI>
|
|
<B>VT9 -- Vertical Total (bit 9)</B></LI>
|
|
|
|
<BR>Specifies bit 9 of the Vertical Total field. See the <A HREF="#06">Vertical
|
|
Total Register</A> for details.
|
|
<LI>
|
|
<B>LC8 -- Line Compare (bit 8)</B></LI>
|
|
|
|
<BR>Specifies bit 8 of the Line Compare field. See the <A HREF="#18">Line
|
|
Compare Register</A> for details.
|
|
<LI>
|
|
<B>SVB8 -- Start Vertical Blanking (bit 8)</B></LI>
|
|
|
|
<BR>Specifies bit 8 of the Start Vertical Blanking field. See the
|
|
<A HREF="#15">Start Vertical Blanking Register</A> for details.
|
|
<LI>
|
|
<B>VRS8 -- Vertical Retrace Start (bit 8)</B></LI>
|
|
|
|
<BR>Specifies bit 8 of the Vertical Retrace Start field. See the
|
|
<A HREF="#10">Vertical Retrace Start Register</A> for details.
|
|
<LI>
|
|
<B>VDE8 -- Vertical Display End (bit 8)</B></LI>
|
|
|
|
<BR>Specifies bit 8 of the Vertical Display End field. See the <A HREF="#12">Vertical
|
|
Display End Register</A> for details.
|
|
<LI>
|
|
<B>VT8 -- Vertical Total (bit 8)</B></LI>
|
|
|
|
<BR>Specifies bit 8 of the Vertical Total field. See the <A HREF="#06">Vertical
|
|
Total Register</A> for details.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="08"></A><B>Preset Row Scan Register (Index
|
|
08h)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75"></TD>
|
|
|
|
<TD COLSPAN="2" WIDTH="150">Byte Panning</TD>
|
|
|
|
<TD COLSPAN="5" WIDTH="375">Preset Row Scan</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>Byte Panning</B></LI>
|
|
|
|
<BR>The value of this field is added to the <A HREF="crtcreg.htm#0D">Start
|
|
Address Register</A> when calculating the display memory address for the
|
|
upper left hand pixel or character of the screen. This allows for a maximum
|
|
shift of 15, 31, or 35 pixels without having to reprogram the <A HREF="crtcreg.htm#0D">Start
|
|
Address Register</A>.
|
|
<LI>
|
|
<B>Preset Row Scan</B></LI>
|
|
|
|
<BR>This field is used when using text mode or any mode with a non-zero
|
|
<A HREF="crtcreg.htm#09">Maximum Scan Line</A> field to provide for more
|
|
precise vertical scrolling than the <A HREF="crtcreg.htm#0D">Start Address
|
|
Register</A> provides. The value of this field specifies how many scan
|
|
lines to scroll the display upwards. Valid values range from 0 to the value
|
|
of the <A HREF="crtcreg.htm#09">Maximum Scan Line</A> field. Invalid values
|
|
may cause undesired effects and seem to be dependent upon the particular
|
|
VGA implementation.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="09"></A><B>Maximum Scan Line Register (Index
|
|
09h)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">SD</TD>
|
|
|
|
<TD WIDTH="75">LC9</TD>
|
|
|
|
<TD WIDTH="75">SVB9</TD>
|
|
|
|
<TD COLSPAN="5" WIDTH="375">Maximum Scan Line</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL><B>SD -- Scan Doubling<BR>
|
|
</B>"<I>When this bit is set to 1, 200-scan-line video data is converted
|
|
to 400-scan-line output. To do this, the clock in the row scan counter
|
|
is divided by 2, which allows the 200-line modes to be displayed as 400
|
|
lines on the display (this is called double scanning; each line is displayed
|
|
twice). When this bit is set to 0, the clock to the row scan counter is
|
|
equal to the horizontal scan rate.</I>"
|
|
<LI>
|
|
<B>LC9 -- Line Compare (bit 9)</B></LI>
|
|
|
|
<BR>Specifies bit 9 of the Line Compare field. See the <A HREF="#18">Line
|
|
Compare Register</A> for details.
|
|
<LI>
|
|
<B>SVB9 -- Start Vertical Blanking (bit 9)</B></LI>
|
|
|
|
<BR>Specifies bit 9 of the Start Vertical Blanking field. See the
|
|
<A HREF="#15">Start Vertical Blanking Register</A> for details.
|
|
<LI>
|
|
<B>Maximum Scan Line</B></LI>
|
|
|
|
<BR>In text modes, this field is programmed with the character height -
|
|
1 (scan line numbers are zero based.) In graphics modes, a non-zero value
|
|
in this field will cause each scan line to be repeated by the value of
|
|
this field + 1.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="0A"></A><B>Cursor Start Register (Index 0Ah)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75"></TD>
|
|
|
|
<TD WIDTH="75"></TD>
|
|
|
|
<TD WIDTH="75">CD</TD>
|
|
|
|
<TD COLSPAN="5" WIDTH="375">Cursor Scan Line Start</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>CD -- Cursor Disable</B></LI>
|
|
|
|
<BR>This field controls whether or not the text-mode cursor is displayed.
|
|
Values are:
|
|
<UL>
|
|
<LI>
|
|
0 -- Cursor Enabled</LI>
|
|
|
|
<LI>
|
|
1 -- Cursor Disabled</LI>
|
|
</UL>
|
|
|
|
<LI>
|
|
<B>Cursor Scan Line Start</B></LI>
|
|
|
|
<BR>This field controls the appearance of the text-mode cursor by specifying
|
|
the scan line location within a character cell at which the cursor should
|
|
begin, with the top-most scan line in a character cell being 0 and the
|
|
bottom being with the value of the <A HREF="#09">Maximum Scan Line</A>
|
|
field.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP> <A NAME="0B"></A><B>Cursor End Register (Index
|
|
0Bh)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75"></TD>
|
|
|
|
<TD COLSPAN="2" WIDTH="150">Cursor Skew</TD>
|
|
|
|
<TD COLSPAN="5" WIDTH="375">Cursor Scan Line End</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>CSK -- Cursor Skew</B></LI>
|
|
|
|
<BR>This field was necessary in the EGA to synchronize the cursor with
|
|
internal timing. In the VGA it basically is added to the cursor location.
|
|
In some cases when this value is non-zero and the cursor is near the left
|
|
or right edge of the screen, the cursor will not appear at all, or a second
|
|
cursor above and to the left of the actual one may appear. This behavior
|
|
may not be the same on all VGA compatible adapter cards.
|
|
<LI>
|
|
<B>Cursor Scan Line End</B></LI>
|
|
|
|
<BR>This field controls the appearance of the text-mode cursor by specifying
|
|
the scan line location within a character cell at which the cursor should
|
|
end, with the top-most scan line in a character cell being 0 and the bottom
|
|
being with the value of the <A HREF="#09">Maximum Scan Line</A> field.
|
|
If this field is less than the <A HREF="#0A">Cursor Scan Line Start</A>
|
|
field, the cursor is not drawn. Some graphics adapters, such as the IBM
|
|
EGA display a split-block cursor instead.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="0C"></A><B>Start Address High Register (Index
|
|
0Ch)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD COLSPAN="8" WIDTH="600">Start Address High</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>Start Address High</B></LI>
|
|
|
|
<BR>This contains specifies bits 15-8 of the Start Address field. See the
|
|
<A HREF="#0D">Start Address Low Register</A> for details.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="0D"></A><B>Start Address Low Register (Index
|
|
0Dh)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD COLSPAN="8" WIDTH="600">Start Address Low</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>Start Address Low</B></LI>
|
|
|
|
<BR>This contains the bits 7-0 of the Start Address field. The upper 8
|
|
bits are specified by the <A HREF="#0C">Start Address High Register</A>.
|
|
The Start Address field specifies the display memory address of the upper
|
|
left pixel or character of the screen. Because the standard VGA has a maximum
|
|
of 256K of memory, and memory is accessed 32 bits at a time, this 16-bit
|
|
field is sufficient to allow the screen to start at any memory address.
|
|
Normally this field is programmed to 0h, except when using virtual resolutions,
|
|
paging, and/or split-screen operation. Note that the VGA display will wrap
|
|
around in display memory if the starting address is too high. (This may
|
|
or may not be desirable, depending on your intentions.)</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION><A NAME="0E"></A><B>Cursor Location High Register (Index 0Eh)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD COLSPAN="8" WIDTH="600">Cursor Location High</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>Cursor Location High</B></LI>
|
|
|
|
<BR>This field specifies bits 15-8 of the Cursor Location field. See the
|
|
<A HREF="#0F">Cursor Location Low Register</A> for details.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="0F"></A><B>Cursor Location Low Register (Index
|
|
0Fh)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD COLSPAN="8" WIDTH="600">Cursor Location Low</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>Cursor Location Low</B></LI>
|
|
|
|
<BR>This field specifies bits 7-0 of the Cursor Location field. When the
|
|
VGA hardware is displaying text mode and the text-mode cursor is enabled,
|
|
the hardware compares the address of the character currently being displayed
|
|
with sum of value of this field and the sum of the <A HREF="#0B">Cursor
|
|
Skew</A> field. If the values equal then the scan lines in that character
|
|
specified by the <A HREF="#0A">Cursor Scan Line Start</A> field and the
|
|
<A HREF="#0B">Cursor Scan Line End</A> field are replaced with the foreground
|
|
color.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="10"></A><B>Vertical Retrace Start Register
|
|
(Index 10h)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD COLSPAN="8" WIDTH="600">Vertical Retrace Start</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>Vertical Retrace Start</B></LI>
|
|
|
|
<BR>This field specifies bits 7-0 of the Vertical Retrace Start field.
|
|
Bits 9-8 are located in the <A HREF="#07">Overflow Register</A>.
|
|
This field controls the start of the vertical retrace pulse which signals
|
|
the display to move up to the beginning of the active display. This
|
|
field contains the value of the vertical scanline counter at the beginning
|
|
of the first scanline where the vertical retrace signal is asserted.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="11"></A><B>Vertical Retrace End Register (Index
|
|
11h)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">Protect</TD>
|
|
|
|
<TD WIDTH="75">Bandwidth</TD>
|
|
|
|
<TD WIDTH="75"></TD>
|
|
|
|
<TD WIDTH="75"></TD>
|
|
|
|
<TD COLSPAN="4" WIDTH="300">Vertical Retrace End</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>Protect -- CRTC Registers Protect Enable</B></LI>
|
|
|
|
<BR>This field is used to protect the video timing registers from being
|
|
changed by programs written for earlier graphics chipsets that attempt
|
|
to program these registers with values unsuitable for VGA timings.
|
|
When this field is set to 1, the CRTC register indexes 00h-07h ignore write
|
|
access, with the exception of bit 4 of the <A HREF="#07">Overflow Register</A>,
|
|
which holds bit 8 of the <A HREF="#18">Line Compare</A> field.
|
|
<LI>
|
|
<B>Bandwidth -- Memory Refresh Bandwidth</B></LI>
|
|
|
|
<BR>Nearly all video chipsets include a few registers that control memory,
|
|
bus, or other timings not directly related to the output of the video card.
|
|
Most VGA/SVGA implementations ignore the value of this field; however,
|
|
in the least, IBM VGA adapters do utilize it and thus for compatibility
|
|
with these chipsets this field should be programmed. This register
|
|
is used in the IBM VGA hardware to control the number of DRAM refresh cycles
|
|
per scan line. The three refresh cycles per scanline is appropriate
|
|
for the IBM VGA horizontal frequency of approximately 31.5 kHz. For
|
|
horizontal frequencies greater than this, this setting will work as the
|
|
DRAM will be refreshed more often. However, refreshing not often
|
|
enough for the DRAM can cause memory loss. Thus at some point slower
|
|
than 31.5 kHz the five refresh cycle setting should be used. At which
|
|
particular point this should occur, would require better knowledge of the
|
|
IBM VGA's schematics than I have available. According to IBM documentation,
|
|
"<I>Selecting five refresh cycles allows use of the VGA chip with 15.75
|
|
kHz displays.</I>" which isn't really enough to go by unless the mode you
|
|
are defining has a 15.75 kHz horizontal frequency.
|
|
<LI>
|
|
<B>Vertical Retrace End</B></LI>
|
|
|
|
<BR>This field determines the end of the vertical retrace pulse, and thus
|
|
its length. This field contains the lower four bits of the vertical
|
|
scanline counter at the beginning of the scanline immediately after the
|
|
last scanline where the vertical retrace signal is asserted.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="12"></A><B>Vertical Display End Register (Index
|
|
12h)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD COLSPAN="8" WIDTH="600">Vertical Display End</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>Vertical Display End</B></LI>
|
|
|
|
<BR>This contains the bits 7-0 of the Vertical Display End field.
|
|
Bits 9-8 are located in the <A HREF="#07">Overflow Register</A>.
|
|
The field contains the value of the vertical scanline counter at the beggining
|
|
of the scanline immediately after the last scanline of active display.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="13"></A><B>Offset Register (Index 13h)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD COLSPAN="8" WIDTH="600">Offset</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>Offset</B></LI>
|
|
|
|
<BR>This field specifies the address difference between consecutive scan
|
|
lines or two lines of characters. Beginning with the second scan line,
|
|
the starting scan line is increased by twice the value of this register
|
|
multiplied by the current memory address size (byte = 1, word = 2, double-word
|
|
= 4) each line. For text modes the following equation is used:
|
|
<BR> <B>Offset = Width / ( MemoryAddressSize
|
|
* 2 )</B>
|
|
<BR>and in graphics mode, the following equation is used:
|
|
<BR> <B>Offset = Width
|
|
/ ( PixelsPerAddress * MemoryAddressSize * 2 )</B>
|
|
<BR>where Width is the width in pixels of the screen. This register can
|
|
be modified to provide for a virtual resolution, in which case Width is
|
|
the width is the width in pixels of the virtual screen. PixelsPerAddress
|
|
is the number of pixels stored in one display memory address, and MemoryAddressSize
|
|
is the current memory addressing size.</UL>
|
|
|
|
<BR>
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="14"></A><B>Underline Location Register (Index
|
|
14h)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75"></TD>
|
|
|
|
<TD WIDTH="75">DW</TD>
|
|
|
|
<TD WIDTH="75">DIV4</TD>
|
|
|
|
<TD COLSPAN="5" WIDTH="375">Underline Location</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL><B>DW - Double-Word Addressing<BR>
|
|
</B>"<I>When this bit is set to 1, memory addresses are doubleword addresses.
|
|
See the description of the word/byte mode bit (bit 6) in the CRT Mode Control
|
|
Register</I>"
|
|
<BR><B>DIV4 - Divide Memory Address Clock by 4<BR>
|
|
</B>"<I>When this bit is set to 1, the memory-address counter is clocked
|
|
with the character clock divided by 4, which is used when doubleword addresses
|
|
are used.</I>"
|
|
<BR><B>Underline Location<BR>
|
|
</B>"<I>These bits specify the horizontal scan line of a character row
|
|
on which an underline occurs. The value programmed is the scan line desired
|
|
minus 1.</I>"</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="15"></A><B>Start Vertical Blanking Register
|
|
(Index 15h)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD COLSPAN="8" WIDTH="600">Start Vertical Blanking</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>Start Vertical Blanking</B></LI>
|
|
|
|
<BR>This contains bits 7-0 of the Start Vertical Blanking field.
|
|
Bit 8 of this field is located in the <A HREF="#07">Overflow Register</A>,
|
|
and bit 9 is located in the <A HREF="#09">Maximum Scan Line Register</A>.
|
|
This field determines when the vertical blanking period begins, and contains
|
|
the value of the vertical scanline counter at the beginning of the first
|
|
vertical scanline of blanking.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="16"></A><B>End Vertical Blanking Register (Index
|
|
16h)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75"></TD>
|
|
|
|
<TD COLSPAN="7" WIDTH="525">End Vertical Blanking</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>End Vertical Blanking</B></LI>
|
|
|
|
<BR>This field determines when the vertical blanking period ends, and contains
|
|
the value of the vertical scanline counter at the beginning of the vertical
|
|
scanline immediately after the last scanline of blanking.</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="17"></A><B>CRTC Mode Control Register (Index
|
|
17h)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">SE</TD>
|
|
|
|
<TD WIDTH="75">Word/Byte</TD>
|
|
|
|
<TD WIDTH="75">AW</TD>
|
|
|
|
<TD WIDTH="75"></TD>
|
|
|
|
<TD WIDTH="75">DIV2</TD>
|
|
|
|
<TD WIDTH="75">SLDIV</TD>
|
|
|
|
<TD WIDTH="75">MAP14</TD>
|
|
|
|
<TD WIDTH="75">MAP13</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL><B>SE -- Sync Enable<BR>
|
|
</B>"<I>When set to 0, this bit disables the horizontal and vertical retrace
|
|
signals and forces them to an inactive level. When set to 1, this bit enables
|
|
the horizontal and vertical retrace signals. This bit does not reset any
|
|
other registers or signal outputs.</I>"
|
|
<BR><B>Word/Byte -- Word/Byte Mode Select<BR>
|
|
</B>"<I>When this bit is set to 0, the word mode is selected. The word
|
|
mode shifts the memory-address counter bits to the left by one bit; the
|
|
most-significant bit of the counter appears on the least-significant bit
|
|
of the memory address outputs. The doubleword bit in the Underline
|
|
Location register (0x14) also controls the addressing. When the doubleword
|
|
bit is 0, the word/byte bit selects the mode. When the doubleword bit is
|
|
set to 1, the addressing is shifted by two bits. When set to 1, bit 6 selects
|
|
the byte address mode.</I>"
|
|
<BR><B>AW -- Address Wrap Select<BR>
|
|
</B>"<I>This bit selects the memory-address bit, bit MA 13 or MA 15, that
|
|
appears on the output pin MA 0, in the word address mode. If the VGA is
|
|
not in the word address mode, bit 0 from the address counter appears on
|
|
the output pin, MA 0. When set to 1, this bit selects MA 15. In odd/even
|
|
mode, this bit should be set to 1 because 256KB of video memory is installed
|
|
on the system board. (Bit MA 13 is selected in applications where only
|
|
64KB is present. This function maintains compatibility with the IBM Color/Graphics
|
|
Monitor Adapter.)</I>"
|
|
<BR><B>DIV2 -- Divide Memory Address clock by 2<BR>
|
|
</B>"<I>When this bit is set to 0, the address counter uses the character
|
|
clock. When this bit is set to 1, the address counter uses the character
|
|
clock input divided by 2. This bit is used to create either a byte or word
|
|
refresh address for the display buffer.</I>"
|
|
<BR><B>SLDIV -- Divide Scan Line clock by 2<BR>
|
|
</B>"<I>This bit selects the clock that controls the vertical timing counter.
|
|
The clocking is either the horizontal retrace clock or horizontal retrace
|
|
clock divided by 2. When this bit is set to 1. the horizontal retrace clock
|
|
is divided by 2. Dividing the clock effectively doubles the vertical resolution
|
|
of the CRT controller. The vertical counter has a maximum resolution of
|
|
1024 scan lines because the vertical total value is 10-bits wide. If the
|
|
vertical counter is clocked with the horizontal retrace divided by 2, the
|
|
vertical resolution is doubled to 2048 scan lines.</I>"
|
|
<BR><B>MAP14 -- Map Display Address 14<BR>
|
|
</B>"<I>This bit selects the source of bit 14 of the output multiplexer.
|
|
When this bit is set to 0, bit 1 of the row scan counter is the source.
|
|
When this bit is set to 1, the bit 14 of the address counter is the source.</I>"
|
|
<BR><B>MAP13 -- Map Display Address 13<BR>
|
|
</B>"<I>This bit selects the source of bit 13 of the output multiplexer.
|
|
When this bit is set to 0, bit 0 of the row scan counter is the source,
|
|
and when this bit is set to 1, bit 13 of the address counter is the source.
|
|
The CRT controller used on the IBM Color/Graphics Adapter was capable of
|
|
using 128 horizontal scan-line addresses. For the VGA to obtain 640-by-200
|
|
graphics resolution, the CRT controller is programmed for 100 horizontal
|
|
scan lines with two scan-line addresses per character row. Row scan
|
|
address bit 0 becomes the most-significant address bit to the display buffer.
|
|
Successive scan lines of the display image are displaced in 8KB of
|
|
memory. This bit allows compatibility with the graphics modes of earlier
|
|
adapters.</I>"</UL>
|
|
|
|
<TABLE BORDER WIDTH="600" CELLPADING="2" >
|
|
<CAPTION ALIGN=TOP><A NAME="18"></A><B>Line Compare Register (Index 18h)</B></CAPTION>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD WIDTH="75">7</TD>
|
|
|
|
<TD WIDTH="75">6</TD>
|
|
|
|
<TD WIDTH="75">5</TD>
|
|
|
|
<TD WIDTH="75">4</TD>
|
|
|
|
<TD WIDTH="75">3</TD>
|
|
|
|
<TD WIDTH="75">2</TD>
|
|
|
|
<TD WIDTH="75">1</TD>
|
|
|
|
<TD WIDTH="75">0</TD>
|
|
</TR>
|
|
|
|
<TR ALIGN=CENTER VALIGN=CENTER>
|
|
<TD COLSPAN="8" WIDTH="600">Line Compare Register</TD>
|
|
</TR>
|
|
</TABLE>
|
|
|
|
<UL>
|
|
<LI>
|
|
<B>Line Compare Register</B></LI>
|
|
|
|
<BR>This field specifies bits 7-0 of the Line Compare field. Bit 9 of this
|
|
field is located in the <A HREF="#09">Maximum Scan Line Register</A>, and
|
|
bit 8 of this field is located in the <A HREF="#07">Overflow Register</A>.
|
|
The Line Compare field specifies the scan line at which a horizontal division
|
|
can occur, providing for split-screen operation. If no horizontal division
|
|
is required, this field should be set to 3FFh. When the scan line counter
|
|
reaches the value in the Line Compare field, the current scan line address
|
|
is reset to 0 and the Preset Row Scan is presumed to be 0. If the <A HREF="attrreg.htm#10">Pixel
|
|
Panning Mode</A> field is set to 1 then the Pixel Shift Count and Byte
|
|
Panning fields are reset to 0 for the remainder of the display cycle.</UL>
|
|
Notice: All trademarks used or referred to on this page are the property
|
|
of their respective owners.
|
|
<BR>All pages are Copyright © 1997, 1998, J. D. Neal, except where
|
|
noted. Permission for utilization and distribution
|
|
<BR>is subject to the terms of the <A HREF="license.htm">FreeVGA Project
|
|
Copyright License</A>.
|
|
</BODY>
|
|
</HTML>
|