361 lines
9.6 KiB
HTML
361 lines
9.6 KiB
HTML
<HTML>
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<HEAD>
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<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
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<META NAME="Author" CONTENT="Joshua Neal">
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<META NAME="Description" CONTENT="Pure VGA/SVGA hardware programming (registers, identification, and other low-level stuff.)">
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<META NAME="KeyWords" CONTENT="VGA SVGA hardware video programming">
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<TITLE>VGA/SVGA Video Programming--Attribute Controller Registers</TITLE>
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</HEAD>
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<BODY>
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<CENTER><A HREF="../home.htm">Home</A> <A HREF="vga.htm#register">Back</A>
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<HR WIDTH="100%"><B>Hardware Level VGA and SVGA Video Programming Information
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Page</B></CENTER>
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<CENTER>Attribute Controller Registers
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<HR WIDTH="100%"></CENTER>
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<P> The Attribute Controller
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Registers are accessed via a pair of registers, the Attribute Address/Data
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Register and the Attribute Data Read Register. See the <A HREF="vgareg.htm">Accessing
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the VGA Registers</A> section for more detals. The Address/Data Register
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is located at port 3C0h and the Data Read Register is located at port 3C1h.
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<BR>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION><A NAME="3C0"></A><B>Attribute Address Register(3C0h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75">PAS</TD>
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<TD COLSPAN="5" WIDTH="375">Attribute Address</TD>
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</TR>
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</TABLE>
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<UL><B>PAS -- Palette Address Source<BR>
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</B>"<I>This bit is set to 0 to load color values to the registers in the
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internal palette. It is set to 1 for normal operation of the attribute
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controller. Note: Do not access the internal palette while this bit is
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set to 1. While this bit is 1, the Type 1 video subsystem disables accesses
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to the palette; however, the Type 2 does not, and the actual color value
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addressed cannot be ensured.</I>"
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<LI>
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<B>Attribute Address<BR>
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</B>This field specifies the index value of the attribute register to be
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read or written.</LI>
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</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="000F"></A><B>Palette Registers (Index 00-0Fh)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD COLSPAN="6" WIDTH="450">Internal Palette Index</TD>
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</TR>
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</TABLE>
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<UL><B>Internal Palette Index<BR>
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</B>"<I>These 6-bit registers allow a dynamic mapping between the text
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attribute or graphic color input value and the display color on the CRT
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screen. When set to 1, this bit selects the appropriate color. The Internal
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Palette registers should be modified only during the vertical retrace interval
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to avoid problems with the displayed image. These internal palette values
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are sent off-chip to the video DAC, where they serve as addresses into
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the DAC registers.</I>"</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="10"></A><B>Attribute Mode Control Register
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(Index 10h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">P54S</TD>
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<TD WIDTH="75">8BIT</TD>
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<TD WIDTH="75">PPM</TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75">BLINK</TD>
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<TD WIDTH="75">LGE</TD>
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<TD WIDTH="75">MONO</TD>
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<TD WIDTH="75">ATGE</TD>
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</TR>
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</TABLE>
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<UL><B>P54S -- Palette Bits 5-4 Select<BR>
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</B>"<I>This bit selects the source for the P5 and P4 video bits that act
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as inputs to the video DAC. When this bit is set to 0, P5 and P4 are the
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outputs of the Internal Palette registers. When this bit is set to 1, P5
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and P4 are bits 1 and 0 of the Color Select register.</I>"
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<BR><B>8BIT -- 8-bit Color Enable<BR>
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</B>"<I>When this bit is set to 1, the video data is sampled so that eight
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bits are available to select a color in the 256-color mode (0x13). This
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bit is set to 0 in all other modes.</I>"
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<LI>
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<B>PPM -- Pixel Panning Mode</B></LI>
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<BR>This field allows the upper half of the screen to pan independently
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of the lower screen. If this field is set to 0 then nothing special occurs
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during a successful line compare (see the <A HREF="crtcreg.htm#18">Line
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Compare</A> field.) If this field is set to 1, then upon a successful line
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compare, the bottom portion of the screen is displayed as if the <A HREF="attrreg.htm#13">Pixel
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Shift Count</A> and <A HREF="crtcreg.htm#08">Byte Panning</A> fields are
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set to 0.
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<BR><B>BLINK - Blink Enable<BR>
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</B>"<I>When this bit is set to 0, the most-significant bit of the attribute
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selects the background intensity (allows 16 colors for background). When
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set to 1, this bit enables blinking.</I>"
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<LI>
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<B>LGA - Line Graphics Enable</B></LI>
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<BR>This field is used in 9 bit wide character modes to provide continuity
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for the horizontal line characters in the range C0h-DFh. If this field
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is set to 0, then the 9th column of these characters is replicated from
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the 8th column of the character. Otherwise, if it is set to 1 then the
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9th column is set to the background like the rest of the characters.
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<LI>
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<B>MONO - Monochrome Emulation</B></LI>
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<BR>This field is used to store your favorite bit. According to IBM, "When
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this bit is set to 1, monochrome emulation mode is selected. When this
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bit is set to 0, color |emulation mode is selected." It is present and
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programmable in all of the hardware but it apparently does nothing. The
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internal palette is used to provide monochrome emulation instead.
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<LI>
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<B>ATGE - Attribute Controller Graphics Enable<BR>
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</B>"<I>When set to 1, this bit selects the graphics mode of operation.</I>"</LI>
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</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION><A NAME="11"></A><B>Overscan Color Register (Index 11h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD COLSPAN="8" WIDTH="600">Overscan Palette Index</TD>
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</TR>
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</TABLE>
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<UL><B>Overscan Palette Index<BR>
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</B>"<I>These bits select the border color used in the 80-column alphanumeric
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modes and in the graphics modes other than modes 4, 5, and D. (Selects
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a color from one of the DAC registers.)</I>"</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="12"></A><B>Color Plane Enable Register (Index
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12h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD COLSPAN="4" WIDTH="300">Color Plane Enable</TD>
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</TR>
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</TABLE>
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<UL>
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<LI>
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<B>Color Plane Enable<BR>
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</B>"<I>Setting a bit to 1, enables the corresponding display-memory color
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plane.</I>"</LI>
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</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="13"></A><B>Horizontal Pixel Panning Register
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(Index 13h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD COLSPAN="4" WIDTH="300">Pixel Shift Count</TD>
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</TR>
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</TABLE>
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<UL><B>Pixel Shift Count<BR>
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</B>"<I>These bits select the number of pels that the video data is shifted
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to the left. PEL panning is available in both alphanumeric and graphics
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modes.</I>"</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="14"></A><B>Color Select Register (Index 14h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD COLSPAN="2" WIDTH="150">Color Select 7-6</TD>
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<TD COLSPAN="2" WIDTH="150">Color Select 5-4</TD>
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</TR>
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</TABLE>
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<UL><B>Color Select 7-6<BR>
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</B>"<I>In modes other than mode 13 hex, these are the two most-significant
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bits of the 8-bit digital color value to the video DAC. In mode 13 hex,
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the 8-bit attribute is the digital color value to the video DAC. These
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bits are used to rapidly switch between sets of colors in the video DAC.</I>"
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<BR><B>Color Select 5-4<BR>
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</B>"<I>These bits can be used in place of the P4 and P5 bits from the
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Internal Palette registers to form the 8-bit digital color value
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to the video DAC. Selecting these bits is done in the Attribute Mode Control
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register (index 0x10). These bits are used to rapidly switch between colors
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sets within the video DAC.</I>"</UL>
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Notice: All trademarks used or referred to on this page are the property
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of their respective owners.
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<BR>All pages are Copyright © 1997, 1998, J. D. Neal, except where
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noted. Permission for utilization and distribution is subject to the terms
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of the <A HREF="license.htm">FreeVGA Project Copyright License</A>.
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</BODY>
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</HTML>
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