refactor: single definition for common registers

src/main/wacc/backend/assemblyIR.scala

@@ -213,4 +213,19 @@ object assemblyIR {
       case String => "%s"
     }
   }
+
+  object commonRegisters {
+    import Size._
+    import RegName._
+
+    val RAX = Register(Q64, AX)
+    val EAX = Register(D32, AX)
+    val RDI = Register(Q64, DI)
+    val RIP = Register(Q64, IP)
+    val RBP = Register(Q64, BP)
+    val RSI = Register(Q64, SI)
+    val RDX = Register(Q64, DX)
+    val RCX = Register(Q64, CX)
+    val ECX = Register(D32, CX)
+  }
 }