From c3f2ce8b197de1bf16e32e01be63f3e51f488261 Mon Sep 17 00:00:00 2001
From: Gleb Koval <gleb@koval.net>
Date: Fri, 28 Feb 2025 14:47:47 +0000
Subject: [PATCH] refactor: single definition for common registers

---
 src/main/wacc/backend/RuntimeError.scala | 10 +---------
 src/main/wacc/backend/asmGenerator.scala | 10 +---------
 src/main/wacc/backend/assemblyIR.scala   | 15 +++++++++++++++
 3 files changed, 17 insertions(+), 18 deletions(-)

diff --git a/src/main/wacc/backend/RuntimeError.scala b/src/main/wacc/backend/RuntimeError.scala
index 8159485..4e4cd07 100644
--- a/src/main/wacc/backend/RuntimeError.scala
+++ b/src/main/wacc/backend/RuntimeError.scala
@@ -19,17 +19,9 @@ sealed trait RuntimeError {
 }
 
 object RuntimeError {
-
-  // TODO: Refactor to mitigate imports and redeclared vals perhaps
-
   import wacc.asmGenerator.stackAlign
-  import assemblyIR.Size._
-  import assemblyIR.RegName._
+  import assemblyIR.commonRegisters._
 
-  private val RDI = Register(Q64, DI)
-  private val RIP = Register(Q64, IP)
-  private val RSI = Register(Q64, SI)
-  private val RCX = Register(Q64, CX)
   private val ERROR_CODE = 255
 
   case object ZeroDivError extends RuntimeError {
diff --git a/src/main/wacc/backend/asmGenerator.scala b/src/main/wacc/backend/asmGenerator.scala
index 3c4ae64..1ae9dc4 100644
--- a/src/main/wacc/backend/asmGenerator.scala
+++ b/src/main/wacc/backend/asmGenerator.scala
@@ -8,21 +8,13 @@ import wacc.RuntimeError._
 object asmGenerator {
   import microWacc._
   import assemblyIR._
+  import assemblyIR.commonRegisters._
   import assemblyIR.Size._
   import assemblyIR.RegName._
   import types._
   import sizeExtensions._
   import lexer.escapedChars
 
-  private val RAX = Register(Q64, AX)
-  private val EAX = Register(D32, AX)
-  private val RDI = Register(Q64, DI)
-  private val RIP = Register(Q64, IP)
-  private val RBP = Register(Q64, BP)
-  private val RSI = Register(Q64, SI)
-  private val RDX = Register(Q64, DX)
-  private val RCX = Register(Q64, CX)
-  private val ECX = Register(D32, CX)
   private val argRegs = List(DI, SI, DX, CX, R8, R9)
 
   private val _7_BIT_MASK = 0x7f
diff --git a/src/main/wacc/backend/assemblyIR.scala b/src/main/wacc/backend/assemblyIR.scala
index e8e7e62..b96325e 100644
--- a/src/main/wacc/backend/assemblyIR.scala
+++ b/src/main/wacc/backend/assemblyIR.scala
@@ -213,4 +213,19 @@ object assemblyIR {
       case String => "%s"
     }
   }
+
+  object commonRegisters {
+    import Size._
+    import RegName._
+
+    val RAX = Register(Q64, AX)
+    val EAX = Register(D32, AX)
+    val RDI = Register(Q64, DI)
+    val RIP = Register(Q64, IP)
+    val RBP = Register(Q64, BP)
+    val RSI = Register(Q64, SI)
+    val RDX = Register(Q64, DX)
+    val RCX = Register(Q64, CX)
+    val ECX = Register(D32, CX)
+  }
 }