refactor: single definition for common registers

src/main/wacc/backend/asmGenerator.scala

@@ -8,21 +8,13 @@ import wacc.RuntimeError._
 object asmGenerator {
   import microWacc._
   import assemblyIR._
+  import assemblyIR.commonRegisters._
   import assemblyIR.Size._
   import assemblyIR.RegName._
   import types._
   import sizeExtensions._
   import lexer.escapedChars
 
-  private val RAX = Register(Q64, AX)
-  private val EAX = Register(D32, AX)
-  private val RDI = Register(Q64, DI)
-  private val RIP = Register(Q64, IP)
-  private val RBP = Register(Q64, BP)
-  private val RSI = Register(Q64, SI)
-  private val RDX = Register(Q64, DX)
-  private val RCX = Register(Q64, CX)
-  private val ECX = Register(D32, CX)
   private val argRegs = List(DI, SI, DX, CX, R8, R9)
 
   private val _7_BIT_MASK = 0x7f