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refactor: replace explicit loops and flatMap with foldMap

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This commit is contained in:
Jonny 2025-02-25 22:46:48 +00:00
parent da0ef9ec24
commit f76b7a9dc2
1 changed files with 6 additions and 6 deletions
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12
src/main/wacc/backend/asmGenerator.scala
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@ -170,11 +170,11 @@ object asmGenerator {
chain += stack.drop() chain += stack.drop()
chain += Jump(LabelArg(elseLabel), Cond.Equal) chain += Jump(LabelArg(elseLabel), Cond.Equal)
chain ++= Chain.fromSeq(thenBranch).flatMap(generateStmt) chain ++= thenBranch.foldMap(generateStmt)
chain += Jump(LabelArg(endLabel)) chain += Jump(LabelArg(endLabel))
chain += LabelDef(elseLabel) chain += LabelDef(elseLabel)
chain ++= Chain.fromSeq(elseBranch).flatMap(generateStmt) chain ++= elseBranch.foldMap(generateStmt)
chain += LabelDef(endLabel) chain += LabelDef(endLabel)
case While(cond, body) => case While(cond, body) =>
@ -187,7 +187,7 @@ object asmGenerator {
chain += stack.drop() chain += stack.drop()
chain += Jump(LabelArg(endLabel), Cond.Equal) chain += Jump(LabelArg(endLabel), Cond.Equal)
chain ++= Chain.fromSeq(body).flatMap(generateStmt) chain ++= body.foldMap(generateStmt)
chain += Jump(LabelArg(startLabel)) chain += Jump(LabelArg(startLabel))
chain += LabelDef(endLabel) chain += LabelDef(endLabel)
@ -298,13 +298,13 @@ object asmGenerator {
val argRegs = List(RDI, RSI, RDX, RCX, R8, R9) val argRegs = List(RDI, RSI, RDX, RCX, R8, R9)
val microWacc.Call(target, args) = call val microWacc.Call(target, args) = call
argRegs.zip(args).foreach { (reg, expr) => argRegs.zip(args).foldMap { (reg, expr) =>
chain ++= evalExprOntoStack(expr) chain ++= evalExprOntoStack(expr)
chain += stack.pop(reg) chain += stack.pop(reg)
} }
args.drop(argRegs.size).foreach { expr => args.drop(argRegs.size).foldMap {
chain ++= evalExprOntoStack(expr) chain ++= evalExprOntoStack(_)
} }
chain += assemblyIR.Call(LabelArg(labelGenerator.getLabel(target))) chain += assemblyIR.Call(LabelArg(labelGenerator.getLabel(target)))