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style: improve code formatting and consistency in typeChecker and assemblyIR

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This commit is contained in:
Guy C 2025-02-25 00:05:10 +00:00
parent 1488281223
commit f30cf42c4b
3 changed files with 147 additions and 138 deletions
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45
src/main/wacc/backend/asmGenerator.scala
View File

@ -19,7 +19,7 @@ object asmGenerator {
val RBP = Register(RegSize.R64, RegName.BP)
val RSI = Register(RegSize.R64, RegName.SI)
val _8_BIT_MASK = 0xFF
val _8_BIT_MASK = 0xff
object labelGenerator {
var labelVal = -1
@ -27,8 +27,8 @@ object asmGenerator {
labelVal += 1
s".L$labelVal"
}
def getLabel(target: CallTarget): String = target match{
case Ident(v,_) => s"wacc_$v"
def getLabel(target: CallTarget): String = target match {
case Ident(v, _) => s"wacc_$v"
case Builtin(name) => s"_$name"
}
}
@ -70,24 +70,22 @@ object asmGenerator {
stack: LinkedHashMap[Ident, Int],
strings: ListBuffer[String]
): List[AsmLine] = {
wrapFunc(labelGenerator.getLabel(Builtin.Exit),
wrapFunc(
labelGenerator.getLabel(Builtin.Exit),
alignStack() ++
List(Pop(RDI),
assemblyIR.Call(CLibFunc.Exit))
List(Pop(RDI), assemblyIR.Call(CLibFunc.Exit))
) ++
wrapFunc(labelGenerator.getLabel(Builtin.Printf),
wrapFunc(
labelGenerator.getLabel(Builtin.Printf),
alignStack() ++
List(assemblyIR.Call(CLibFunc.PrintF),
List(
assemblyIR.Call(CLibFunc.PrintF),
Move(RDI, ImmediateVal(0)),
assemblyIR.Call(CLibFunc.Fflush)
)
)++
wrapFunc(labelGenerator.getLabel(Builtin.Malloc),
List()
)++
wrapFunc(labelGenerator.getLabel(Builtin.Free),
List()
)
) ++
wrapFunc(labelGenerator.getLabel(Builtin.Malloc), List()) ++
wrapFunc(labelGenerator.getLabel(Builtin.Free), List())
}
def generateStmt(
@ -191,14 +189,16 @@ object asmGenerator {
case BoolLiter(v) => List(Push(ImmediateVal(if (v) 1 else 0)))
case NullLiter() => List(Push(ImmediateVal(0)))
case ArrayElem(value, indices) => List()
case UnaryOp(x, op) => op match {
case UnaryOp(x, op) =>
op match {
// TODO: chr and ord are TYPE CASTS. They do not change the internal value,
// but will need bound checking e.t.c.
case UnaryOperator.Chr => List()
case UnaryOperator.Ord => List()
case UnaryOperator.Len => List()
case UnaryOperator.Negate => List(
Negate(MemLocation(RSP,SizeDir.Word))
case UnaryOperator.Negate =>
List(
Negate(MemLocation(RSP, SizeDir.Word))
)
case UnaryOperator.Not =>
evalExprOntoStack(x) ++
@ -207,7 +207,8 @@ object asmGenerator {
)
}
case BinaryOp(x, y, op) => op match {
case BinaryOp(x, y, op) =>
op match {
case BinaryOperator.Add =>
evalExprOntoStack(x) ++
evalExprOntoStack(y) ++
@ -269,14 +270,14 @@ object asmGenerator {
evalExprOntoStack(y) ++
List(
Pop(EAX),
And(MemLocation(RSP, SizeDir.Word), EAX),
And(MemLocation(RSP, SizeDir.Word), EAX)
)
case BinaryOperator.Or =>
evalExprOntoStack(x) ++
evalExprOntoStack(y) ++
List(
Pop(EAX),
Or(MemLocation(RSP, SizeDir.Word), EAX),
Or(MemLocation(RSP, SizeDir.Word), EAX)
)
}
case microWacc.Call(target, args) => List()
@ -308,7 +309,7 @@ object asmGenerator {
// }
def generateComparison(x : Expr, y: Expr, cond: Cond)(using
def generateComparison(x: Expr, y: Expr, cond: Cond)(using
stack: LinkedHashMap[Ident, Int],
strings: ListBuffer[String]
): List[AsmLine] = {

16
src/main/wacc/backend/assemblyIR.scala
View File

@ -19,7 +19,8 @@ object assemblyIR {
}
enum RegName {
case AX, AL, BX, CX, DX, SI, DI, SP, BP, IP, Reg8, Reg9, Reg10, Reg11, Reg12, Reg13, Reg14, Reg15
case AX, AL, BX, CX, DX, SI, DI, SP, BP, IP, Reg8, Reg9, Reg10, Reg11, Reg12, Reg13, Reg14,
Reg15
override def toString = this match {
case AX => "ax"
case AL => "al"
@ -59,17 +60,24 @@ object assemblyIR {
}
}
//TODO register naming conventions are wrong
// TODO register naming conventions are wrong
case class Register(size: RegSize, name: RegName) extends Dest with Src {
override def toString = s"${size}${name}"
}
case class MemLocation(pointer: Long | Register, opSize: SizeDir = SizeDir.Unspecified) extends Dest with Src {
case class MemLocation(pointer: Long | Register, opSize: SizeDir = SizeDir.Unspecified)
extends Dest
with Src {
override def toString = pointer match {
case hex: Long => opSize.toString + f"[0x$hex%X]"
case reg: Register => opSize.toString + s"[$reg]"
}
}
case class IndexAddress(base: Register, offset: Int | LabelArg, opSize: SizeDir = SizeDir.Unspecified) extends Dest with Src {
case class IndexAddress(
base: Register,
offset: Int | LabelArg,
opSize: SizeDir = SizeDir.Unspecified
) extends Dest
with Src {
override def toString = s"$opSize[$base + $offset]"
}