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style: improve code formatting and consistency in typeChecker and assemblyIR

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This commit is contained in:
Guy C 2025-02-25 00:05:10 +00:00
parent 1488281223
commit f30cf42c4b
3 changed files with 147 additions and 138 deletions
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35
src/main/wacc/backend/asmGenerator.scala
View File

@ -19,7 +19,7 @@ object asmGenerator {
val RBP = Register(RegSize.R64, RegName.BP) val RBP = Register(RegSize.R64, RegName.BP)
val RSI = Register(RegSize.R64, RegName.SI) val RSI = Register(RegSize.R64, RegName.SI)
val _8_BIT_MASK = 0xFF val _8_BIT_MASK = 0xff
object labelGenerator { object labelGenerator {
var labelVal = -1 var labelVal = -1
@ -70,24 +70,22 @@ object asmGenerator {
stack: LinkedHashMap[Ident, Int], stack: LinkedHashMap[Ident, Int],
strings: ListBuffer[String] strings: ListBuffer[String]
): List[AsmLine] = { ): List[AsmLine] = {
wrapFunc(labelGenerator.getLabel(Builtin.Exit), wrapFunc(
labelGenerator.getLabel(Builtin.Exit),
alignStack() ++ alignStack() ++
List(Pop(RDI), List(Pop(RDI), assemblyIR.Call(CLibFunc.Exit))
assemblyIR.Call(CLibFunc.Exit))
) ++ ) ++
wrapFunc(labelGenerator.getLabel(Builtin.Printf), wrapFunc(
labelGenerator.getLabel(Builtin.Printf),
alignStack() ++ alignStack() ++
List(assemblyIR.Call(CLibFunc.PrintF), List(
assemblyIR.Call(CLibFunc.PrintF),
Move(RDI, ImmediateVal(0)), Move(RDI, ImmediateVal(0)),
assemblyIR.Call(CLibFunc.Fflush) assemblyIR.Call(CLibFunc.Fflush)
) )
) ++ ) ++
wrapFunc(labelGenerator.getLabel(Builtin.Malloc), wrapFunc(labelGenerator.getLabel(Builtin.Malloc), List()) ++
List() wrapFunc(labelGenerator.getLabel(Builtin.Free), List())
)++
wrapFunc(labelGenerator.getLabel(Builtin.Free),
List()
)
} }
def generateStmt( def generateStmt(
@ -191,13 +189,15 @@ object asmGenerator {
case BoolLiter(v) => List(Push(ImmediateVal(if (v) 1 else 0))) case BoolLiter(v) => List(Push(ImmediateVal(if (v) 1 else 0)))
case NullLiter() => List(Push(ImmediateVal(0))) case NullLiter() => List(Push(ImmediateVal(0)))
case ArrayElem(value, indices) => List() case ArrayElem(value, indices) => List()
case UnaryOp(x, op) => op match { case UnaryOp(x, op) =>
op match {
// TODO: chr and ord are TYPE CASTS. They do not change the internal value, // TODO: chr and ord are TYPE CASTS. They do not change the internal value,
// but will need bound checking e.t.c. // but will need bound checking e.t.c.
case UnaryOperator.Chr => List() case UnaryOperator.Chr => List()
case UnaryOperator.Ord => List() case UnaryOperator.Ord => List()
case UnaryOperator.Len => List() case UnaryOperator.Len => List()
case UnaryOperator.Negate => List( case UnaryOperator.Negate =>
List(
Negate(MemLocation(RSP, SizeDir.Word)) Negate(MemLocation(RSP, SizeDir.Word))
) )
case UnaryOperator.Not => case UnaryOperator.Not =>
@ -207,7 +207,8 @@ object asmGenerator {
) )
} }
case BinaryOp(x, y, op) => op match { case BinaryOp(x, y, op) =>
op match {
case BinaryOperator.Add => case BinaryOperator.Add =>
evalExprOntoStack(x) ++ evalExprOntoStack(x) ++
evalExprOntoStack(y) ++ evalExprOntoStack(y) ++
@ -269,14 +270,14 @@ object asmGenerator {
evalExprOntoStack(y) ++ evalExprOntoStack(y) ++
List( List(
Pop(EAX), Pop(EAX),
And(MemLocation(RSP, SizeDir.Word), EAX), And(MemLocation(RSP, SizeDir.Word), EAX)
) )
case BinaryOperator.Or => case BinaryOperator.Or =>
evalExprOntoStack(x) ++ evalExprOntoStack(x) ++
evalExprOntoStack(y) ++ evalExprOntoStack(y) ++
List( List(
Pop(EAX), Pop(EAX),
Or(MemLocation(RSP, SizeDir.Word), EAX), Or(MemLocation(RSP, SizeDir.Word), EAX)
) )
} }
case microWacc.Call(target, args) => List() case microWacc.Call(target, args) => List()

14
src/main/wacc/backend/assemblyIR.scala
View File

@ -19,7 +19,8 @@ object assemblyIR {
} }
enum RegName { enum RegName {
case AX, AL, BX, CX, DX, SI, DI, SP, BP, IP, Reg8, Reg9, Reg10, Reg11, Reg12, Reg13, Reg14, Reg15 case AX, AL, BX, CX, DX, SI, DI, SP, BP, IP, Reg8, Reg9, Reg10, Reg11, Reg12, Reg13, Reg14,
Reg15
override def toString = this match { override def toString = this match {
case AX => "ax" case AX => "ax"
case AL => "al" case AL => "al"
@ -63,13 +64,20 @@ object assemblyIR {
case class Register(size: RegSize, name: RegName) extends Dest with Src { case class Register(size: RegSize, name: RegName) extends Dest with Src {
override def toString = s"${size}${name}" override def toString = s"${size}${name}"
} }
case class MemLocation(pointer: Long | Register, opSize: SizeDir = SizeDir.Unspecified) extends Dest with Src { case class MemLocation(pointer: Long | Register, opSize: SizeDir = SizeDir.Unspecified)
extends Dest
with Src {
override def toString = pointer match { override def toString = pointer match {
case hex: Long => opSize.toString + f"[0x$hex%X]" case hex: Long => opSize.toString + f"[0x$hex%X]"
case reg: Register => opSize.toString + s"[$reg]" case reg: Register => opSize.toString + s"[$reg]"
} }
} }
case class IndexAddress(base: Register, offset: Int | LabelArg, opSize: SizeDir = SizeDir.Unspecified) extends Dest with Src { case class IndexAddress(
base: Register,
offset: Int | LabelArg,
opSize: SizeDir = SizeDir.Unspecified
) extends Dest
with Src {
override def toString = s"$opSize[$base + $offset]" override def toString = s"$opSize[$base + $offset]"
} }