diff --git a/src/main/wacc/backend/asmGenerator.scala b/src/main/wacc/backend/asmGenerator.scala index 7440791..ab350f4 100644 --- a/src/main/wacc/backend/asmGenerator.scala +++ b/src/main/wacc/backend/asmGenerator.scala @@ -30,11 +30,16 @@ object asmGenerator { } //TODO - def generateFuncs()(using stack: LinkedHashMap[Ident, Int], strings: ListBuffer[String]): List[AsmLine] = { + def generateFuncs()(using + stack: LinkedHashMap[Ident, Int], + strings: ListBuffer[String] + ): List[AsmLine] = { List() } - def generateStmt(stmt: Stmt)(using stack: LinkedHashMap[Ident, Int], strings: ListBuffer[String]): List[AsmLine] = + def generateStmt( + stmt: Stmt + )(using stack: LinkedHashMap[Ident, Int], strings: ListBuffer[String]): List[AsmLine] = stmt match { case microWacc.Call(Builtin.Exit, code :: _) => alignStack() ++ @@ -47,9 +52,10 @@ object asmGenerator { List( assemblyIR.Call(CLibFunc.Puts), Move(Register(RegSize.R64, RegName.DI), ImmediateVal(0)), - assemblyIR.Call(CLibFunc.Fflush)) ++ - restoreStack() - + assemblyIR.Call(CLibFunc.Fflush) + ) ++ + restoreStack() + case microWacc.Call(Builtin.ReadInt, expr :: _) => List() @@ -64,8 +70,10 @@ object asmGenerator { case _ => List() } - def evalExprIntoReg(expr: Expr, dest: Register) - (using stack: LinkedHashMap[Ident, Int], strings: ListBuffer[String]): List[AsmLine] = { + def evalExprIntoReg(expr: Expr, dest: Register)(using + stack: LinkedHashMap[Ident, Int], + strings: ListBuffer[String] + ): List[AsmLine] = { var src: Src = ImmediateVal(0) // Placeholder (expr match { case IntLiter(v) => @@ -78,14 +86,21 @@ object asmGenerator { IndexAddress(Register(RegSize.R64, RegName.SP), (stack.size - stack(ident)) * 4) ) ) - case ArrayLiter(elems) => expr.ty match { - case KnownType.Char => - strings += elems.mkString - List( - Load(dest, IndexAddress(Register(RegSize.R64, RegName.IP),LabelArg(s".L.str${strings.size - 1}"))) - ) - case _ => List() - } + case ArrayLiter(elems) => + expr.ty match { + case KnownType.Char => + strings += elems.mkString + List( + Load( + dest, + IndexAddress( + Register(RegSize.R64, RegName.IP), + LabelArg(s".L.str${strings.size - 1}") + ) + ) + ) + case _ => List() + } case _ => List() }) ++ List(Move(dest, src)) } diff --git a/src/main/wacc/backend/assemblyIR.scala b/src/main/wacc/backend/assemblyIR.scala index e1b16ee..73cdeaf 100644 --- a/src/main/wacc/backend/assemblyIR.scala +++ b/src/main/wacc/backend/assemblyIR.scala @@ -98,7 +98,8 @@ object assemblyIR { case class Call(op1: CLibFunc | LabelArg) extends Operation("call", op1) case class Move(op1: Dest, op2: Src) extends Operation("mov", op1, op2) - case class Load(op1: Register, op2: MemLocation | IndexAddress) extends Operation("lea ", op1, op2) + case class Load(op1: Register, op2: MemLocation | IndexAddress) + extends Operation("lea ", op1, op2) case class Return() extends Operation("ret")