From 8ed94e4df3e3a8e8bdcd6bfcb57ceb6ac6231bad Mon Sep 17 00:00:00 2001
From: Alex Ling <al4423@ic.ac.uk>
Date: Tue, 25 Feb 2025 03:17:05 +0000
Subject: [PATCH] fix: initial exprs on stack

---
 src/main/wacc/backend/asmGenerator.scala | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/main/wacc/backend/asmGenerator.scala b/src/main/wacc/backend/asmGenerator.scala
index 2a4a2ad..0e8eb55 100644
--- a/src/main/wacc/backend/asmGenerator.scala
+++ b/src/main/wacc/backend/asmGenerator.scala
@@ -111,8 +111,8 @@ object asmGenerator {
   )(using stack: LinkedHashMap[Ident, Int], strings: ListBuffer[String]): List[AsmLine] =
     stmt match {
       case Assign(lhs, rhs) =>
-        var dest: IndexAddress =
-          IndexAddress(RSP, 0) // gets overrwitten
+        var dest: () => IndexAddress =
+          () => IndexAddress(RSP, 0) // gets overrwitten
         (lhs match {
           case ident: Ident =>
             if (!stack.contains(ident)) {
@@ -129,7 +129,9 @@ object asmGenerator {
             List()
         }) ++
           evalExprOntoStack(rhs) ++
-          List(Pop(dest))
+          List(Pop(RAX),
+          Move(dest(), RAX),
+          )
       case If(cond, thenBranch, elseBranch) => {
         val elseLabel = labelGenerator.getLabel()
         val endLabel = labelGenerator.getLabel()
@@ -173,7 +175,7 @@ object asmGenerator {
       case CharLiter(v) =>
         List(Push(ImmediateVal(v.toInt)))
       case ident: Ident =>
-        List(Push(accessVar(ident)))
+        List(Push(accessVar(ident)()))
       case ArrayLiter(elems) =>
         expr.ty match {
           case KnownType.String =>
@@ -347,11 +349,12 @@ object asmGenerator {
         Compare(MemLocation(RSP, SizeDir.Word), EAX),
         Set(Register(RegSize.Byte, RegName.AL), cond),
         And(EAX, ImmediateVal(_8_BIT_MASK)),
+        Load(RSP, IndexAddress(RSP, 8)),
         Push(RAX)
       )
   }
-  def accessVar(ident: Ident)(using stack: LinkedHashMap[Ident, Int]): IndexAddress =
-    IndexAddress(RSP, (stack.size - stack(ident)) * 8)
+  def accessVar(ident: Ident)(using stack: LinkedHashMap[Ident, Int]): () => IndexAddress =
+    () => IndexAddress(RSP, (stack.size - stack(ident)) * 8)
 
   def alignStack()(using stack: LinkedHashMap[Ident, Int]): List[AsmLine] = {
     List(