diff --git a/src/main/wacc/backend/assemblyIR.scala b/src/main/wacc/backend/assemblyIR.scala
index 0d167c2..323742b 100644
--- a/src/main/wacc/backend/assemblyIR.scala
+++ b/src/main/wacc/backend/assemblyIR.scala
@@ -2,6 +2,7 @@ package wacc
 
 object assemblyIR {
 
+  sealed trait AsmLine
   sealed trait Operand
   sealed trait Src extends Operand // mem location, register and imm value
   sealed trait Dest extends Operand // mem location and register
@@ -58,7 +59,7 @@ object assemblyIR {
   }
 
   // TODO Check if dest and src are not both memory locations
-  abstract class Operation(ins: String, ops: Operand*) {
+  abstract class Operation(ins: String, ops: Operand*) extends AsmLine {
     override def toString: String = s"\t$ins ${ops.mkString(", ")}"
   }
   case class Add(op1: Dest, op2: Src) extends Operation("add", op1, op2)
@@ -83,7 +84,7 @@ object assemblyIR {
   case class Jump(op1: LabelArg, condition: Cond = Cond.Always)
       extends Operation(s"j${condition.toString}", op1)
 
-  case class LabelDef(name: String) {
+  case class LabelDef(name: String) extends AsmLine {
     override def toString = s"$name:"
   }
 
diff --git a/src/main/wacc/backend/writer.scala b/src/main/wacc/backend/writer.scala
new file mode 100644
index 0000000..b798af3
--- /dev/null
+++ b/src/main/wacc/backend/writer.scala
@@ -0,0 +1,11 @@
+package wacc
+
+import java.io.PrintStream
+
+object writer {
+  import assemblyIR._
+
+  def writeTo(asmList: List[AsmLine], printStream: PrintStream): Unit = {
+    asmList.foreach(printStream.println)
+  }
+}