diff --git a/src/test/wacc/instructionSpec.scala b/src/test/wacc/instructionSpec.scala
new file mode 100644
index 0000000..6d427a5
--- /dev/null
+++ b/src/test/wacc/instructionSpec.scala
@@ -0,0 +1,65 @@
+import org.scalatest.funsuite.AnyFunSuite
+import wacc.assemblyIR._
+
+class instructionSpec extends AnyFunSuite {
+
+  val named64BitRegister = Register.Named("ax", RegSize.R64)
+
+  test("named 64-bit register toString") {
+    assert(named64BitRegister.toString == "rax")
+  }
+
+  val named32BitRegister = Register.Named("ax", RegSize.E32)
+
+  test("named 32-bit register toString") {
+    assert(named32BitRegister.toString == "eax")
+  }
+
+  val scratch64BitRegister = Register.Scratch(1, RegSize.R64)
+
+  test("scratch 64-bit register toString") {
+    assert(scratch64BitRegister.toString == "r1")
+  }
+
+  val scratch32BitRegister = Register.Scratch(1, RegSize.E32)
+
+  test("scratch 32-bit register toString") {
+    assert(scratch32BitRegister.toString == "r1d")
+  }
+
+  val memLocationWithHex = MemLocation(0x12345678)
+
+  test("mem location with hex toString") {
+    assert(memLocationWithHex.toString == "[0x12345678]")
+  }
+
+  val memLocationWithRegister = MemLocation(named64BitRegister)
+
+  test("mem location with register toString") {
+    assert(memLocationWithRegister.toString == "[rax]")
+  }
+
+  val immediateVal = ImmediateVal(123)
+
+  test("immediate value toString") {
+    assert(immediateVal.toString == "123")
+  }
+
+  val addInstruction = Add(named64BitRegister, immediateVal)
+
+  test("x86: add instruction toString") {
+    assert(addInstruction.toString == "\tadd rax, 123")
+  }
+
+  val subInstruction = Subtract(scratch64BitRegister, named64BitRegister)
+
+  test("x86: sub instruction toString") {
+    assert(subInstruction.toString == "\tsub r1, rax")
+  }
+
+  val callInstruction = Call(CLibFunc.Scanf)
+
+  test("x86: call instruction toString") {
+    assert(callInstruction.toString == "\tcall scanf@plt")
+  }
+}