feat: incomplete initial implementation of assemblyIR
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parent
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68
src/main/wacc/backend/assemblyIR.scala
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68
src/main/wacc/backend/assemblyIR.scala
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package wacc
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object assemblyIR {
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enum RegSize {
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case R64
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case E32
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override def toString: String = this match {
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case R64 => "r"
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case E32 => "e"
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}
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}
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enum CLibFunc {
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case Scanf,
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Puts,
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Fflush,
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Exit,
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PrintF
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private val plt = "@plt"
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override def toString: String = this match {
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case Scanf => "scanf" + plt
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case Puts => "puts" + plt
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case Fflush => "fflush" + plt
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case Exit => "exit" + plt
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case PrintF => "printf" + plt
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}
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}
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enum Register {
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case Named(name: String, size: RegSize)
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case Scratch(num: Int, size: RegSize)
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override def toString: String = this match {
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case Named(name, size) => s"${size}${name}"
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case Scratch(num, size) => s"${size}${num}"
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}
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}
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case class MemLocation(pointer: Long)
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case class ImmediateVal(value: Int)
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//TODO Check if dest and src are not both memory locations
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sealed trait noDupeMemLoc
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// object noDupeMemLoc {
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// def apply(dest: Register | MemLocation, src: Register | MemLocation | ImmediateVal) : noDupeMemLoc {
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// require(!(dest.isInstanceOf[MemLocation] && src.isInstanceOf[MemLocation]))
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// }
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// }
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case class Add(dest: Register | MemLocation, src: Register | MemLocation | ImmediateVal) extends noDupeMemLoc
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case class Subtract(dest: Register | MemLocation, src: Register | MemLocation | ImmediateVal) extends noDupeMemLoc
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case class Multiply(src: Register)
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case class Divide(src: Register)
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case class And(dest: Register | MemLocation, src: Register | MemLocation | ImmediateVal) extends noDupeMemLoc
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case class Or(dest: Register | MemLocation, src: Register | MemLocation | ImmediateVal) extends noDupeMemLoc
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case class Compare(dest: Register | MemLocation, src: Register | MemLocation | ImmediateVal) extends noDupeMemLoc
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case class Call(func: CLibFunc)
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case class Push(src: Register | MemLocation | ImmediateVal)
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case class Pop(src: Register | MemLocation | ImmediateVal)
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case class Jump()
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}
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