From 1ce36dd8da8e4b217dfce542f63968353a642a25 Mon Sep 17 00:00:00 2001 From: Barf-Vader <47476490+Barf-Vader@users.noreply.github.com> Date: Fri, 21 Feb 2025 23:34:37 +0000 Subject: [PATCH] refactor: unit tests now work with asm ir refactor --- src/test/wacc/instructionSpec.scala | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/test/wacc/instructionSpec.scala b/src/test/wacc/instructionSpec.scala index 6d427a5..b7452a0 100644 --- a/src/test/wacc/instructionSpec.scala +++ b/src/test/wacc/instructionSpec.scala @@ -3,28 +3,28 @@ import wacc.assemblyIR._ class instructionSpec extends AnyFunSuite { - val named64BitRegister = Register.Named("ax", RegSize.R64) + val named64BitRegister = Register(RegSize.R64, RegName.AX) test("named 64-bit register toString") { assert(named64BitRegister.toString == "rax") } - val named32BitRegister = Register.Named("ax", RegSize.E32) + val named32BitRegister = Register(RegSize.E32, RegName.AX) test("named 32-bit register toString") { assert(named32BitRegister.toString == "eax") } - val scratch64BitRegister = Register.Scratch(1, RegSize.R64) + val scratch64BitRegister = Register(RegSize.R64, RegName.Reg8) test("scratch 64-bit register toString") { - assert(scratch64BitRegister.toString == "r1") + assert(scratch64BitRegister.toString == "r8") } - val scratch32BitRegister = Register.Scratch(1, RegSize.E32) + val scratch32BitRegister = Register(RegSize.E32, RegName.Reg8) test("scratch 32-bit register toString") { - assert(scratch32BitRegister.toString == "r1d") + assert(scratch32BitRegister.toString == "e8") } val memLocationWithHex = MemLocation(0x12345678) @@ -54,7 +54,7 @@ class instructionSpec extends AnyFunSuite { val subInstruction = Subtract(scratch64BitRegister, named64BitRegister) test("x86: sub instruction toString") { - assert(subInstruction.toString == "\tsub r1, rax") + assert(subInstruction.toString == "\tsub r8, rax") } val callInstruction = Call(CLibFunc.Scanf)