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fix: generate strDirs after prog, change += to +

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This commit is contained in:
Gleb Koval 2025-02-25 21:05:21 +00:00
parent ebc65af981
commit 11c483439c
Signed by: cyclane
GPG Key ID: 15E168A8B332382C
1 changed files with 11 additions and 23 deletions
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34
src/main/wacc/backend/asmGenerator.scala
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@ -28,7 +28,7 @@ object asmGenerator {
val _8_BIT_MASK = 0xff
extension (chain: Chain[AsmLine])
def +=(line: AsmLine): Chain[AsmLine] = chain.append(line)
def +(line: AsmLine): Chain[AsmLine] = chain.append(line)
def concatAll(chains: Chain[AsmLine]*): Chain[AsmLine] =
chains.foldLeft(chain)(_ ++ _)
@ -51,14 +51,6 @@ object asmGenerator {
given labelGenerator: LabelGenerator = LabelGenerator()
val Program(funcs, main) = microProg
val strDirs = strings.toList.zipWithIndex.foldMap { case (str, i) =>
Chain(
Directive.Int(str.size),
LabelDef(s".L.str$i"),
Directive.Asciz(str.escaped)
)
}
val progAsm = Chain(LabelDef("main")).concatAll(
funcPrologue(),
Chain.one(stack.align()),
@ -68,6 +60,14 @@ object asmGenerator {
generateBuiltInFuncs()
)
val strDirs = strings.toList.zipWithIndex.foldMap { case (str, i) =>
Chain(
Directive.Int(str.size),
LabelDef(s".L.str$i"),
Directive.Asciz(str.escaped)
)
}
Chain(
Directive.IntelSyntax,
Directive.Global("main"),
@ -328,32 +328,20 @@ object asmGenerator {
// Missing a sub instruction but dont think we need it
def funcPrologue()(using stack: Stack): Chain[AsmLine] = {
val chain = Chain.empty[AsmLine]
var chain = Chain.empty[AsmLine]
chain += stack.push(RBP)
chain += Move(RBP, Register(RegSize.R64, RegName.SP))
chain
}
def funcEpilogue()(using stack: Stack): Chain[AsmLine] = {
val chain = Chain.empty[AsmLine]
var chain = Chain.empty[AsmLine]
chain += Move(Register(RegSize.R64, RegName.SP), RBP)
chain += stack.pop(RBP)
chain += assemblyIR.Return()
chain
}
class LabelGenerator {
var labelVal = -1
def getLabel(): String = {
labelVal += 1
s".L$labelVal"
}
def getLabel(target: CallTarget): String = target match {
case Ident(v, _) => s"wacc_$v"
case Builtin(name) => s"_$name"
}
}
class Stack {
private val stack = LinkedHashMap[Expr | Int, Int]()
private val RSP = Register(RegSize.R64, RegName.SP)