provided code
This commit is contained in:
LabTS
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specs/freevga/vga/vgafunc.htm
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402
specs/freevga/vga/vgafunc.htm
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<HTML>
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<HEAD>
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<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
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<META NAME="Author" CONTENT="Joshua Neal">
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<META NAME="Description" CONTENT="Pure VGA/SVGA hardware programming (registers, identification, and otherlow-level stuff.)">
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<META NAME="KeyWords" CONTENT="VGA SVGA hardware video programming">
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<TITLE>VGA/SVGA Video Programming--VGA Functional Index</TITLE>
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</HEAD>
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<BODY>
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<CENTER><A HREF="../home.htm">Home</A> <A HREF="#register">Register</A>
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<A HREF="#memory">Memory</A> <A HREF="#sequencer">Sequencing</A> <A HREF="#cursor">Cursor</A>
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<A HREF="#attribute">Attribute</A> <A HREF="#DAC">DAC</A> <A HREF="#display">Display</A>
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<A HREF="#misc">Misc</A> <A HREF="vga.htm#index">Back</A>
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<HR WIDTH="100%"><B>Hardware Level VGA and SVGA Video Programming Information
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Page</B></CENTER>
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<CENTER>VGA Functional Index
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<HR WIDTH="100%"></CENTER>
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<P><A NAME="register"></A><B>Register Access Functions</B>
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<BR> These fields control the
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acessability/inaccessability of the VGA registers. These registers are
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used for compatibiltiy with older programs that may attempt to program
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the VGA in a fashion suited only to an EGA, CGA, or monochrome card.
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<UL>
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<LI>
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CRTC Registers Protect Enable -- <A HREF="crtcreg.htm#11">Vertical Retrace
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End Register</A></LI>
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<LI>
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Enable Vertical Retrace Access -- <A HREF="crtcreg.htm#03">End Horizontal
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Blanking Register</A></LI>
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<LI>
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Input/Output Address Select -- <A HREF="extreg.htm#3CCR3C2W">Miscellaneous
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Output Register</A></LI>
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</UL>
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<A NAME="memory"></A><B>Display Memory Access Functions</B>
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<BR> These fields control the
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way the video RAM is mapped into the host CPU's address space and how memory
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reads/writes affect the display memory.
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<UL>
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<LI>
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Bit Mask -- <A HREF="graphreg.htm#08">Bit Mask Register</A></LI>
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<LI>
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Chain 4 Enable -- <A HREF="seqreg.htm#04">Sequencer Memory Mode Register</A></LI>
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<LI>
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Chain Odd/Even Enable -- <A HREF="graphreg.htm#06">Miscellaneous Graphics
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Register</A></LI>
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<LI>
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Color Compare -- <A HREF="graphreg.htm#02">Color Compare Register</A></LI>
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<LI>
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Color Don't Care -- <A HREF="graphreg.htm#07">Color Don't Care Register</A></LI>
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<LI>
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Enable Set/Reset -- <A HREF="graphreg.htm#01">Enable Set/Reset Register</A></LI>
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<LI>
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Extended Memory -- <A HREF="seqreg.htm#04">Sequencer Memory Mode Register</A></LI>
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<LI>
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Host Odd/Even Memory Read Addressing Enable -- <A HREF="graphreg.htm#05">Graphics
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Mode Register</A></LI>
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<LI>
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Host Odd/Even Memory Write Addressing Enable -- <A HREF="seqreg.htm#04">Sequencer
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Memory Mode Register</A></LI>
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<LI>
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Logical Operation -- <A HREF="graphreg.htm#03">Data Rotate Register</A></LI>
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<LI>
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Memory Map Select -- <A HREF="graphreg.htm#06">Miscellaneous Graphics Register</A></LI>
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<LI>
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Memory Plane Write Enable -- <A HREF="seqreg.htm#02">Map Mask Register</A></LI>
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<LI>
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Odd/Even Page Select -- <A HREF="extreg.htm#3CCR3C2W">Miscellaneous Output
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Register</A></LI>
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<LI>
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RAM Enable -- <A HREF="extreg.htm#3CCR3C2W">Miscellaneous Output Register</A></LI>
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<LI>
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Read Map Select -- <A HREF="graphreg.htm#04">Read Map Select Register</A></LI>
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<LI>
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Read Mode - <A HREF="graphreg.htm#05">Graphics Mode Register</A></LI>
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<LI>
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Rotate Count -- <A HREF="graphreg.htm#03">Data Rotate Register</A></LI>
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<LI>
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Set/Reset -- <A HREF="graphreg.htm#00">Set/Reset Register</A></LI>
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<LI>
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Write Mode -- <A HREF="graphreg.htm#05">Graphics Mode Register</A></LI>
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</UL>
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<A NAME="sequencer"></A><B>Display Sequencing Functions</B>
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<BR> These fields affect the
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way the video memory is serialized for display.
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<UL>
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<LI>
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256-Color Shift Mode -- <A HREF="graphreg.htm#05">Graphics Mode Register</A></LI>
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<LI>
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9/8 Dot Mode -- <A HREF="seqreg.htm#01">Clocking Mode Register</A></LI>
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<LI>
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Address Wrap Select -- <A HREF="crtcreg.htm#17">CRTC Mode Control Register</A></LI>
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<LI>
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Alphanumeric Mode Disable -- <A HREF="graphreg.htm#06">Miscellaneous Graphics
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Register</A></LI>
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<LI>
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Asynchronous Reset -- <A HREF="seqreg.htm#00">Reset Register</A></LI>
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<LI>
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Byte Panning -- <A HREF="crtcreg.htm#08">Preset Row Scan Register</A></LI>
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<LI>
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Character Set A Select -- <A HREF="seqreg.htm#03">Character Map Select
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Register</A></LI>
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<LI>
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Character Set B Select -- <A HREF="seqreg.htm#03">Character Map Select
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Register</A></LI>
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<LI>
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Divide Memory Address Clock by 4 -- <A HREF="crtcreg.htm#14">Underline
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Location Register</A></LI>
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<LI>
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Double-Word Addressing -- <A HREF="crtcreg.htm#14">Underline Location Register</A></LI>
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<LI>
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Pixel Shift Count -- <A HREF="attrreg.htm#13">Horizontal Pixel Panning
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Register</A></LI>
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<LI>
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Line Compare -- bit 9: <A HREF="crtcreg.htm#09">Maximum Scan Line Register</A>,
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bit 8: <A HREF="crtcreg.htm#07">Overflow Register</A>, bits 7-0: <A HREF="crtcreg.htm#18">Line
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Compare Register</A></LI>
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<LI>
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Line Graphics Enable -- <A HREF="attrreg.htm#10">Attribute Mode Control
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Register</A></LI>
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<LI>
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Map Display Address 13 -- <A HREF="crtcreg.htm#17">CRTC Mode Control Register</A></LI>
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<LI>
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Map Display Address 14 -- <A HREF="crtcreg.htm#17">CRTC Mode Control Register</A></LI>
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<LI>
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Maximum Scan Line -- <A HREF="crtcreg.htm#09">Maximum Scan Line Register</A></LI>
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<LI>
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Offset -- <A HREF="crtcreg.htm#13">Offset Register</A></LI>
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<LI>
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Pixel Panning Mode -- <A HREF="attrreg.htm#10">Attribute Mode Control Register</A></LI>
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<LI>
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Preset Row Scan -- <A HREF="crtcreg.htm#08">Preset Row Scan Register</A></LI>
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<LI>
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Scan Doubling -- <A HREF="crtcreg.htm#09">Maximum Scan Line Register</A></LI>
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<LI>
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Screen Disable -- <A HREF="seqreg.htm#01">Clocking Mode Register</A></LI>
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<LI>
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Shift Four Enable -- <A HREF="seqreg.htm#01">Clocking Mode Register</A></LI>
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<LI>
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Shift/Load Rate -- <A HREF="seqreg.htm#01">Clocking Mode Register</A></LI>
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<LI>
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Shift Register Interleave Mode -- <A HREF="graphreg.htm#05">Graphics Mode
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Register</A></LI>
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<LI>
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Start Address -- bits 15-8: <A HREF="crtcreg.htm#0C">Start Address High
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Register</A>, bits 7-0: <A HREF="crtcreg.htm#0D">Start Address Low Register</A></LI>
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<LI>
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Sycnchronous Reset -- <A HREF="seqreg.htm#00">Reset Register</A></LI>
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<LI>
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Word/Byte Mode Select -- <A HREF="crtcreg.htm#17">CRTC Mode Control Register</A></LI>
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</UL>
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<A NAME="cursor"></A><B>Cursor Functions</B>
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<BR> These fields affect the
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operation of the cursor displayed while the VGA hardware is in text mode.
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<UL>
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<LI>
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Cursor Disable -- <A HREF="crtcreg.htm#0A">Cursor Start Reguster</A></LI>
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<LI>
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Cursor Location -- bits 15-8: <A HREF="crtcreg.htm#0E">Cursor Location
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High Register</A>, bits 7-0: <A HREF="crtcreg.htm#0F">Cursor Location Low
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Register</A></LI>
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<LI>
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Cursor Scan Line End -- <A HREF="crtcreg.htm#0B">Cursor End Register</A></LI>
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<LI>
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Cursor Scan Line Start -- <A HREF="crtcreg.htm#0A">Cursor Start Reguster</A></LI>
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<LI>
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Cursor Skew -- <A HREF="crtcreg.htm#0B">Cursor End Register</A></LI>
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</UL>
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<A NAME="attribute"></A><B>Attribute Functions</B>
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<BR> These fields control the
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way the video data is submitted to the RAMDAC, providing color/blinking
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capability in text mode and facilitating the mapping of colors in graphics
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mode.
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<UL>
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<LI>
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8-bit Color Enable -- <A HREF="attrreg.htm#10">Attribute Mode Control Register</A></LI>
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<LI>
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Attribute Address -- <A HREF="attrreg.htm#3C0">Attribute Address Register</A></LI>
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<LI>
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Attribute Controller Graphics Enable -- <A HREF="attrreg.htm#10">Attribute
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Mode Control Register</A></LI>
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<LI>
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Blink Enable -- <A HREF="attrreg.htm#10">Attribute Mode Control Register</A></LI>
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<LI>
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Color Plane Enable -- <A HREF="attrreg.htm#12">Color Plane Enable Register</A></LI>
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<LI>
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Color Select 5-4 -- <A HREF="attrreg.htm#14">Color Select Register</A></LI>
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<LI>
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Color Select 7-6 -- <A HREF="attrreg.htm#14">Color Select Register</A></LI>
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<LI>
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Internal Palette Index -- <A HREF="attrreg.htm#000F">Palette Registers</A></LI>
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<LI>
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Monochrome Emulation -- <A HREF="attrreg.htm#10">Attribute Mode Control
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Register</A></LI>
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<LI>
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Overscan Palette Index -- <A HREF="attrreg.htm#11">Overscan Color Register</A></LI>
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<LI>
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Underline Location -- <A HREF="crtcreg.htm#14">Underline Location Register</A></LI>
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<LI>
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Palette Address Source -- <A HREF="attrreg.htm#3C0">Attribute Address Register</A></LI>
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<LI>
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Palette Bits 5-4 Select -- <A HREF="attrreg.htm#10">Attribute Mode Control
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Register</A></LI>
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</UL>
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<A NAME="DAC"></A><B>DAC Functions</B>
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<BR> These fields allow control
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of the VGA's 256-color palette that is part of the RAMDAC.
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<UL>
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<LI>
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DAC Write Address -- <A HREF="colorreg.htm#3C8">DAC Address Write Mode
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Register</A></LI>
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<LI>
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DAC Read Address -- <A HREF="colorreg.htm#3C7W">DAC Address Read Mode Register</A></LI>
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<LI>
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DAC Data -- <A HREF="colorreg.htm#3C9">DAC Data Register</A></LI>
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<LI>
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DAC State -- <A HREF="colorreg.htm#3C7R">DAC State Register</A></LI>
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</UL>
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<A NAME="display"></A><B>Display Generation Functions</B>
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<BR> These fields control the
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formatting and timing of the VGA's video signal output.
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<UL>
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<LI>
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Clock Select -- <A HREF="extreg.htm#3CCR3C2W">Miscellaneous Output Register</A></LI>
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<LI>
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Display Disabled -- <A HREF="extreg.htm#3xAR">Input Status #1 Register</A></LI>
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<LI>
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Display Enable Skew -- <A HREF="crtcreg.htm#03">End Horizontal Blanking
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Register</A></LI>
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<LI>
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Divide Scan Line Clock by 2 -- <A HREF="crtcreg.htm#17">CRTC Mode Control
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Register</A></LI>
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<LI>
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Dot Clock Rate -- <A HREF="seqreg.htm#01">Clocking Mode Register</A></LI>
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<LI>
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End Horizontal Display -- <A HREF="crtcreg.htm#01">End Horizontal Display
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Register</A></LI>
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<LI>
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End Horizontal Blanking -- bit 5: <A HREF="crtcreg.htm#05">End Horizontal
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Retrace Register</A>, bits 4-0: <A HREF="crtcreg.htm#03">End Horizontal
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Blanking Register</A>,</LI>
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<LI>
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End Horizontal Retrace -- <A HREF="crtcreg.htm#05">End Horizontal Retrace
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Register</A></LI>
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<LI>
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End Vertical Blanking -- <A HREF="crtcreg.htm#16">End Vertical Blanking
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Register</A></LI>
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<LI>
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Horizontal Retrace Skew -- <A HREF="crtcreg.htm#05">End Horizontal Retrace
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Register</A></LI>
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<LI>
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Horizontal Sync Polarity -- <A HREF="extreg.htm#3CCR3C2W">Miscellaneous
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Output Register</A></LI>
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<LI>
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Horizontal Total -- <A HREF="crtcreg.htm#00">Horizontal Total Register</A></LI>
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<LI>
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Memory Refresh Bandwidth -- <A HREF="crtcreg.htm#11">Vertical Retrace End
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Register</A></LI>
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<LI>
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Start Horizontal Blanking -- <A HREF="crtcreg.htm#02">Start Horizontal
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Blanking Register</A></LI>
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<LI>
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Start Horizontal Retrace -- <A HREF="crtcreg.htm#04">Start Horizontal Retrace
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Register</A></LI>
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<LI>
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Start Vertical Blanking -- bit 9: <A HREF="crtcreg.htm#09">Maximum Scan
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Line Register</A>, bit 8: <A HREF="crtcreg.htm#07">Overflow Register</A>,
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bits 7-0: <A HREF="crtcreg.htm#15">Start Vertical Blanking Register</A></LI>
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<LI>
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Sync Enable -- <A HREF="crtcreg.htm#17">CRTC Mode Control Register</A></LI>
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<LI>
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Vertical Display End -- bits 9-8: <A HREF="crtcreg.htm#07">Overflow Register</A>,
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bits 7-0: <A HREF="crtcreg.htm#12">Vertical Display End Register</A></LI>
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<LI>
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Vertical Retrace End -- <A HREF="crtcreg.htm#11">Vertical Retrace End Register</A></LI>
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<LI>
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Vertical Retrace -- <A HREF="extreg.htm#3xAR">Input Status #1 Register</A></LI>
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<LI>
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Vertical Retrace Start -- bits 9-8: <A HREF="crtcreg.htm#07">Overflow Register</A>,
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bits 7-0: <A HREF="crtcreg.htm#10">Vertical Retrace Start Register</A></LI>
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<LI>
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Vertical Sync Polarity -- <A HREF="extreg.htm#3CCR3C2W">Miscellaneous Output
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Register</A></LI>
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<LI>
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Vertical Total -- bits 9-8: <A HREF="crtcreg.htm#07">Overflow Register</A>,
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bits 7-0: <A HREF="crtcreg.htm#06">Vertical Total Register</A></LI>
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</UL>
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<A NAME="misc"></A><B>Miscellaneous Functions</B>
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<BR> These fields are used to
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detect the state of possible VGA hardware such as configuration switches/jumpers
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and feature connector inputs.
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<UL>
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<LI>
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Feature Control Bit 0 -- <A HREF="extreg.htm#3CAR3xAW">Feature Control
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Register</A></LI>
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<LI>
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Feature Control Bit 1 -- <A HREF="extreg.htm#3CAR3xAW">Feature Control
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Register</A></LI>
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<LI>
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Switch Sense -- <A HREF="extreg.htm#3C2R">Input Status #0 Register</A></LI>
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</UL>
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Notice: All trademarks used or referred to on this page are the property
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of their respective owners.
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<BR>All pages are Copyright © 1997, 1998, J. D. Neal, except where
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noted. Permission for utilization and distribution is subject to the terms
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of the <A HREF="license.htm">FreeVGA Project Copyright License</A>.
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<BR>
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<BR>
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</BODY>
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</HTML>
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