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specs/freevga/vga/seqreg.htm
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381
specs/freevga/vga/seqreg.htm
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<HTML>
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<HEAD>
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<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
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<META NAME="Author" CONTENT="Joshua Neal">
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<META NAME="Description" CONTENT="Pure VGA/SVGA hardware programming (registers, identification, and other low-level stuff.)">
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<META NAME="KeyWords" CONTENT="VGA SVGA hardware video programming">
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<TITLE>VGA/SVGA Video Programming--Sequencer Registers</TITLE>
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</HEAD>
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<BODY>
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<CENTER><A HREF="../home.htm">Home</A> <A HREF="vga.htm#register">Back</A>
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<HR WIDTH="100%"><B>Hardware Level VGA and SVGA Video Programming Information
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Page</B></CENTER>
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<CENTER>Sequencer Registers
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<HR WIDTH="100%"></CENTER>
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<P> The Sequencer Registers are
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accessed via a pair of registers, the Sequencer Address Register and the
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Sequencer Data Register. See the <A HREF="vgareg.htm">Accessing the VGA
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Registers</A> section for more detals. The Address Register is located
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at port 3C4h and the Data Register is located at port 3C5h.
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<UL>
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<LI>
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Index 00h -- <I>Reset Register</I></LI>
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<LI>
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Index 01h -- <I>Clocking Mode Register</I></LI>
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<LI>
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Index 02h -- <I>Map Mask Register</I></LI>
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<LI>
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Index 03h -- Character Map Select Register</LI>
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<LI>
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Index 04h -- <I>Sequencer Memory Mode Register</I></LI>
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</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="00"></A><B>Reset Register (Index 00h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75">SR</TD>
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<TD WIDTH="75">AR</TD>
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</TR>
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</TABLE>
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<UL><B>SR -- Sychnronous Reset</B>
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<BR>"<I>When set to 0, this bit commands the sequencer to synchronously
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clear and halt. Bits 1 and 0 must be 1 to allow the sequencer to operate.
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To prevent the loss of data, bit 1 must be set to 0 during the active display
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interval before changing the clock selection. The clock is changed through
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the Clocking Mode register or the Miscellaneous Output register.</I>"
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<BR><B>AR -- Asynchronous Reset</B>
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<BR>"<I>When set to 0, this bit commands the sequencer to asynchronously
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clear and halt. Resetting the sequencer with this bit can cause loss of
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video data</I>"</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="01"></A><B>Clocking Mode Register (Index 01h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75">SD</TD>
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<TD WIDTH="75">S4</TD>
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<TD WIDTH="75">DCR</TD>
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<TD WIDTH="75">SLR</TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75">9/8DM</TD>
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</TR>
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</TABLE>
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<UL><B>SD -- Screen Disable</B>
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<BR>"<I>When set to 1, this bit turns off the display and assigns maximum
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memory bandwidth to the system. Although the display is blanked, the synchronization
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pulses are maintained. This bit can be used for rapid full-screen updates.</I>"
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<BR><B>S4 -- Shift Four Enable</B>
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<BR>"<I>When the Shift 4 field and the Shift Load Field are set to 0, the
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video serializers are loaded every character clock. When the Shift 4 field
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is set to 1, the video serializers are loaded every forth character clock,
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which is useful when 32 bits are fetched per cycle and chained together
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in the shift registers.</I>"
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<BR><B>DCR -- Dot Clock Rate</B>
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<BR>"<I>When set to 0, this bit selects the normal dot clocks derived from
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the sequencer master clock input. When this bit is set to 1, the master
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clock will be divided by 2 to generate the dot clock. All other timings
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are affected because they are derived from the dot clock. The dot clock
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divided by 2 is used for 320 and 360 horizontal PEL modes.</I>"
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<BR><B>SLR -- Shift/Load Rate</B>
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<BR>"<I>When this bit and bit 4 are set to 0, the video serializers are
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loaded every character clock. When this bit is set to 1, the video serializers
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are loaded every other character clock, which is useful when 16 bits are
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fetched per cycle and chained together in the shift registers. The Type
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2 video behaves as if this bit is set to 0; therefore, programs should
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set it to 0.</I>"
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<LI>
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<B>9/8DM -- 9/8 Dot Mode</B></LI>
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<BR>This field is used to select whether a character is 8 or 9 dots wide.
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This can be used to select between 720 and 640 pixel modes (or 360 and
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320) and also is used to provide 9 bit wide character fonts in text mode.
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The possible values for this field are:
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<UL>
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<LI>
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0 - Selects 9 dots per character.</LI>
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<LI>
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1 - Selects 8 dots per character.</LI>
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</UL>
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</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="02"></A><B>Map Mask Register (Index 02h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD COLSPAN="4" WIDTH="300">Memory Plane Write Enable</TD>
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</TR>
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</TABLE>
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<UL>
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<LI>
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<B>Memory Plane Write Enable</B></LI>
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<BR>Bits 3-0 of this field correspond to planes 3-0 of the VGA display
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memory. If a bit is set, then write operations will modify the respective
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plane of display memory. If a bit is not set then write operations will
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not affect the respective plane of display memory.</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="03"></A><B>Character Map Select Register (Index
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03h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75">CSAS2</TD>
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<TD WIDTH="75">CSBS2</TD>
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<TD COLSPAN="2" WIDTH="150">Character Set A Select</TD>
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<TD COLSPAN="2" WIDTH="150">Character Set B Select</TD>
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</TR>
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</TABLE>
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<UL>
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<LI>
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<B>CSAS2 -- Bit 2 of Character Set A Select</B></LI>
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<BR>This is bit 2 of the Character Set A Select field. See <A HREF="#03">Character
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Set A Select</A> below.
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<LI>
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<B>CSBS2 -- Bit 2 of Character Set B Select</B></LI>
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<BR>This is bit 2 of the Character Set B field. See <A HREF="#03">Character
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Set B Select</A> below.
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<LI>
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<B>Character Set A Select</B></LI>
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<BR>This field is used to select the font that is used in text mode when
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bit 3 of the attribute byte for a character is set to 1. Note that this
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field is not contiguous in order to provide EGA compatibility. The font
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selected resides in plane 2 of display memory at the address specified
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by this field, as follows:
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<UL>
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<LI>
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000b -- Select font residing at 0000h - 1FFFh</LI>
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</UL>
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<UL>
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<LI>
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001b -- Select font residing at 4000h - 5FFFh</LI>
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<LI>
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010b -- Select font residing at 8000h - 9FFFh</LI>
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<LI>
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011b -- Select font residing at C000h - DFFFh</LI>
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<LI>
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100b -- Select font residing at 2000h - 3FFFh</LI>
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<LI>
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101b -- Select font residing at 6000h - 7FFFh</LI>
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<LI>
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110b -- Select font residing at A000h - BFFFh</LI>
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<LI>
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111b -- Select font residing at E000h - FFFFh</LI>
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</UL>
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<LI>
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<B>Character Set B Select</B></LI>
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<BR>This field is used to select the font that is used in text mode when
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bit 3 of the attribute byte for a character is set to 0. Note that this
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field is not contiguous in order to provide EGA compatibility. The font
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selected resides in plane 2 of display memory at the address specified
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by this field, identical to the mapping used by <A HREF="#03">Character
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Set A Select</A> above.</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="04"></A><B>Sequencer Memory Mode Register (Index
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04h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75">Chain 4</TD>
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<TD WIDTH="75">O/E Dis.</TD>
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<TD WIDTH="75">Ext. Mem</TD>
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<TD WIDTH="75"></TD>
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</TR>
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</TABLE>
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<UL><B>Chain 4 -- Chain 4 Enable</B>
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<BR>"<I>This bit controls the map selected during system read operations.
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When set to 0, this bit enables system addresses to sequentially access
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data within a bit map by using the Map Mask register. When setto 1, this
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bit causes the two low-order bits to select the map accessed as shown below.</I>
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<BR><I>Address Bits</I>
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<BR><I> A0 A1
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Map Selected</I>
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<BR><I> 0 0
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0</I>
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<BR><I> 0 1
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1</I>
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<BR><I> 1 0
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2</I>
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<BR><I> 1 1
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3</I>"
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<BR><B>O/E Dis. -- Odd/Even Host Memory Write Adressing Disable<BR>
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</B>"<I>When this bit is set to 0, even system addresses access maps 0
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and 2, while odd system addresses access maps 1 and 3. When this bit is
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set to 1, system addresses sequentially access data within a bit map, and
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the maps are accessed according to the value in the Map Mask register (index
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0x02).</I>"
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<BR><B>Ext. Mem -- Extended Memory<BR>
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</B>"<I>When set to 1, this bit enables the video memory from 64KB to 256KB.
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This bit must be set to 1 to enable the character map selection described
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for the previous register.</I>"</UL>
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Notice: All trademarks used or referred to on this page are the property
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of their respective owners.
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<BR>All pages are Copyright © 1997, 1998, J. D. Neal, except where
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noted. Permission for utilization and distribution is subject to the terms
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of the <A HREF="license.htm">FreeVGA Project Copyright License</A>.
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</BODY>
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</HTML>
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