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specs/freevga/vga/extreg.htm
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specs/freevga/vga/extreg.htm
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<HTML>
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<HEAD>
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<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
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<META NAME="Author" CONTENT="Joshua Neal">
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<META NAME="Description" CONTENT="Pure VGA/SVGA hardware programming (registers, identification, and other low-level stuff.)">
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<META NAME="KeyWords" CONTENT="VGA SVGA hardware video programming">
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<TITLE>VGA/SVGA Video Programming--External Regsters</TITLE>
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</HEAD>
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<BODY>
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<UL>
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<CENTER><A HREF="../home.htm">Home</A> <A HREF="vga.htm#register">Back</A>
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<HR WIDTH="100%"><B>Hardware Level VGA and SVGA Video Programming Information
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Page</B></CENTER>
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<CENTER>External Regsters</CENTER>
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<CENTER>
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<HR WIDTH="100%"></CENTER>
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</UL>
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The External Registers (sometimes
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called the General Registers) each have their own unique I/O location in
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the VGA, although sometimes the Read Port differs from the Write port,
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and some are Read-only.. See the <A HREF="vgareg.htm">Accessing the VGA
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Registers</A> section for more detals.
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<UL>
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<LI>
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Port 3CCh/3C2h -- <I>Miscellaneous Output Register</I></LI>
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<LI>
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Port 3CAh/3xAh -- <I>Feature Control Register</I></LI>
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<LI>
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Port 3C2h -- <I>Input Status #0 Register</I></LI>
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<LI>
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Port 3xAh -- <I>Input Status #1 Register</I></LI>
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</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="3CCR3C2W"></A><B>Miscellaneous Output Register
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(Read at 3CCh, Write at 3C2h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">VSYNCP</TD>
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<TD WIDTH="75">HSYNCP</TD>
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<TD WIDTH="75">O/E Page</TD>
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<TD WIDTH="75"></TD>
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<TD COLSPAN="2" WIDTH="150">Clock Select</TD>
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<TD WIDTH="75">RAM En.</TD>
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<TD WIDTH="75">I/OAS</TD>
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</TR>
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</TABLE>
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<UL><B>VSYNCP -- Vertical Sync Polarity<BR>
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</B>"<I>Determines the polarity of the vertical sync pulse and can be used
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(with HSP) to control the vertical size of the display by utilizing the
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autosynchronization feature of VGA displays.</I>
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<BR><I> = 0 selects a positive vertical retrace sync pulse.</I>"
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<BR><B>HSYNCP -- Horizontal Sync Polarity<BR>
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</B>"<I>Determines the polarity of the horizontal sync pulse.</I>
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<BR><I> = 0 selects a positive horizontal retrace sync pulse.</I>"
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<BR><B>O/E Page -- Odd/Even Page Select<BR>
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</B>"<I>Selects the upper/lower 64K page of memory when the system is in
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an eve/odd mode (modes 0,1,2,3,7).</I>
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<BR><I> = 0 selects the low page</I>
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<BR><I> = 1 selects the high page</I>"
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<LI>
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<B>Clock Select</B></LI>
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<BR>This field controls the selection of the dot clocks used in driving
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the display timing. The standard hardware has 2 clocks available
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to it, nominally 25 Mhz and 28 Mhz. It is possible that there may
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be other "external" clocks that can be selected by programming this register
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with the undefined values. The possible valuse of this register are:
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<UL>
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<LI>
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00 -- select 25 Mhz clock (used for 320/640 pixel wide modes)</LI>
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<LI>
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01 -- select 28 Mhz clock (used for 360/720 pixel wide modes)</LI>
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<LI>
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10 -- undefined (possible external clock)</LI>
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<LI>
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11 -- undefined (possible external clock)</LI>
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</UL>
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<B>RAM En. -- RAM Enable<BR>
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</B>"<I>Controls system access to the display buffer.</I>
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<BR><I> = 0 disables address decode for the display buffer from the
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system</I>
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<BR><I> = 1 enables address decode for the display buffer from the
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system</I>"
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<BR><B>I/OAS -- Input/Output Address Select<BR>
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</B>"<I>This bit selects the CRT controller addresses. When set to 0, this
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bit sets the CRT controller addresses to 0x03Bx and the address for the
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Input Status Register 1 to 0x03BA for compatibility withthe monochrome
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adapter. When set to 1, this bit sets CRT controller addresses to
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0x03Dx and the Input Status Register 1 address to 0x03DA for compatibility
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with the color/graphics adapter. The Write addresses to the Feature Control
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register are affected in the same manner.</I>"</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="3CAR3xAW"></A><B>Feature Control Register (Read
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at 3CAh, Write at 3BAh (mono) or 3DAh (color))</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75">FC1</TD>
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<TD WIDTH="75">FC0</TD>
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</TR>
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</TABLE>
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<UL>
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<LI>
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<B>FC1 -- Feature Control bit 1<BR>
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</B>"<I>All bits are reserved.</I>"</LI>
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<LI>
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<B>FC2 -- Feature Control bit 0<BR>
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</B>"<I>All bits are reserved.</I>"</LI>
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</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="3C2R"></A><B>Input Status #0 Register (Read-only
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at 3C2h)</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75">SS</TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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</TR>
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</TABLE>
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<UL><B>SS - Switch Sense<BR>
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</B>"<I>Returns the status of the four sense switches as selected by the
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CS field of the Miscellaneous Output Register.</I>"</UL>
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<TABLE BORDER WIDTH="600" CELLPADING="2" >
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<CAPTION ALIGN=TOP><A NAME="3xAR"></A><B>Input Status #1 Register (Read
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at 3BAh (mono) or 3DAh (color))</B></CAPTION>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75">7</TD>
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<TD WIDTH="75">6</TD>
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<TD WIDTH="75">5</TD>
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<TD WIDTH="75">4</TD>
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<TD WIDTH="75">3</TD>
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<TD WIDTH="75">2</TD>
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<TD WIDTH="75">1</TD>
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<TD WIDTH="75">0</TD>
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</TR>
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<TR ALIGN=CENTER VALIGN=CENTER>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75">VRetrace</TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75"></TD>
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<TD WIDTH="75">DD</TD>
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</TR>
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</TABLE>
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<UL><B>VRetrace -- Vertical Retrace<BR>
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</B>"<I>When set to 1, this bit indicates that the display is in a vertical
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retrace interval.This bit can be programmed, through the Vertical Retrace
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End register, to generate an interrupt at the start of the vertical retrace.</I>"
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<BR><B>DD -- Display Disabled<BR>
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</B>"<I>When set to 1, this bit indicates a horizontal or vertical retrace
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interval. This bit is the real-time status of the inverted 'display enable'
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signal. Programs have used this status bit to restrict screen updates to
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the inactive display intervals in order to reduce screen flicker. The video
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subsystem is designed to eliminate this software requirement; screen updates
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may be made at any time without screen degradation.</I>"</UL>
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Notice: All trademarks used or referred to on this page are the property
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of their respective owners.
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<BR>All pages are Copyright © 1997, 1998, J. D. Neal, except where
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noted. Permission for utilization and distribution is subject to the terms
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of the <A HREF="license.htm">FreeVGA Project Copyright License</A>.
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</BODY>
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</HTML>
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