296 lines
8.9 KiB
Scala
296 lines
8.9 KiB
Scala
package wacc
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import scala.collection.mutable.LinkedHashMap
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import scala.collection.mutable.ListBuffer
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object labelGenerator {
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var labelVal = -1
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def getLabel(): String = {
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labelVal += 1
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s".L$labelVal"
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}
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}
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object asmGenerator {
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import microWacc._
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import assemblyIR._
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import wacc.types._
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def generateAsm(microProg: Program): List[AsmLine] = {
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given stack: LinkedHashMap[Ident, Int] = LinkedHashMap[Ident, Int]()
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given strings: ListBuffer[String] = ListBuffer[String]()
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val Program(funcs, main) = microProg
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val progAsm =
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LabelDef("main") ::
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funcPrologue() ++
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alignStack() ++
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main.flatMap(generateStmt) ++
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funcEpilogue() ++
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List(assemblyIR.Return()) ++
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generateFuncs()
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val strDirs = strings.toList.zipWithIndex.flatMap { case (str, i) =>
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List(Directive.Int(str.size), LabelDef(s".L.str$i"), Directive.Asciz(str))
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}
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List(Directive.IntelSyntax, Directive.Global("main"), Directive.RoData) ++
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strDirs ++
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List(Directive.Text) ++
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progAsm
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}
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//TODO
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def generateFuncs()(using
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stack: LinkedHashMap[Ident, Int],
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strings: ListBuffer[String]
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): List[AsmLine] = {
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List()
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}
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def generateStmt(
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stmt: Stmt
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)(using stack: LinkedHashMap[Ident, Int], strings: ListBuffer[String]): List[AsmLine] =
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stmt match {
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case microWacc.Call(Builtin.Exit, code :: _) =>
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// alignStack() ++
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evalExprIntoReg(code, Register(RegSize.R64, RegName.DI)) ++
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List(assemblyIR.Call(CLibFunc.Exit))
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case microWacc.Call(Builtin.Println, expr :: _) =>
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// alignStack() ++
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printF(expr) ++
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printLn()
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case microWacc.Call(Builtin.Print, expr :: _) =>
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// alignStack() ++
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printF(expr)
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case Assign(lhs, rhs) =>
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var dest: IndexAddress =
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IndexAddress(Register(RegSize.R64, RegName.SP), 0) // gets overrwitten
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(lhs match {
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case ident: Ident =>
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if (!stack.contains(ident)) {
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stack += (ident -> (stack.size + 1))
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dest = accessVar(ident)
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List(Subtract(Register(RegSize.R64, RegName.SP), ImmediateVal(16)))
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} else {
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dest = accessVar(ident)
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List()
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}
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// TODO lhs = arrayElem
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case _ =>
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// dest = ???
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List()
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}) ++
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(rhs match {
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case microWacc.Call(Builtin.ReadInt, _) =>
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readIntoVar(dest, Builtin.ReadInt)
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case microWacc.Call(Builtin.ReadChar, _) =>
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readIntoVar(dest, Builtin.ReadChar)
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case _ =>
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evalExprIntoReg(rhs, Register(RegSize.R64, RegName.AX)) ++
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List(Move(dest, Register(RegSize.R64, RegName.AX)))
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})
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case If(cond, thenBranch, elseBranch) => {
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val elseLabel = labelGenerator.getLabel()
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val endLabel = labelGenerator.getLabel()
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evalExprIntoReg(cond, Register(RegSize.R64, RegName.AX)) ++
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List(
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Compare(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
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Jump(LabelArg(elseLabel), Cond.Equal)
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) ++
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thenBranch.flatMap(generateStmt) ++
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List(Jump(LabelArg(endLabel)), LabelDef(elseLabel)) ++
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elseBranch.flatMap(generateStmt) ++
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List(LabelDef(endLabel))
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}
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case While(cond, body) => {
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val startLabel = labelGenerator.getLabel()
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val endLabel = labelGenerator.getLabel()
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List(LabelDef(startLabel)) ++
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evalExprIntoReg(cond, Register(RegSize.R64, RegName.AX)) ++
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List(
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Compare(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
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Jump(LabelArg(endLabel), Cond.Equal)
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) ++
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body.flatMap(generateStmt) ++
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List(Jump(LabelArg(startLabel)), LabelDef(endLabel))
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}
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case microWacc.Return(expr) =>
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evalExprIntoReg(expr, Register(RegSize.R64, RegName.AX))
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case _ => List()
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}
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def evalExprIntoReg(expr: Expr, dest: Register)(using
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stack: LinkedHashMap[Ident, Int],
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strings: ListBuffer[String]
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): List[AsmLine] = {
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expr match {
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case IntLiter(v) =>
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List(Move(dest, ImmediateVal(v)))
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case CharLiter(v) =>
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List(Move(dest, ImmediateVal(v.toInt)))
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case ident: Ident =>
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List(Move(dest, accessVar(ident)))
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case ArrayLiter(elems) =>
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expr.ty match {
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case KnownType.String =>
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strings += elems.map {
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case CharLiter(v) => v
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case _ => ""
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}.mkString
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List(
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Load(
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dest,
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IndexAddress(
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Register(RegSize.R64, RegName.IP),
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LabelArg(s".L.str${strings.size - 1}")
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)
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)
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)
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// TODO other array types
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case _ => List()
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}
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// TODO other expr types
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case BoolLiter(v) => List(Move(dest, ImmediateVal(if (v) 1 else 0)))
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case _ => List()
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}
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}
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// TODO make sure EOF doenst override the value in the stack
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// probably need labels implemented for conditional jumps
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def readIntoVar(dest: IndexAddress, readType: Builtin.ReadInt.type | Builtin.ReadChar.type)(using
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stack: LinkedHashMap[Ident, Int],
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strings: ListBuffer[String]
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): List[AsmLine] = {
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readType match {
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case Builtin.ReadInt =>
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strings += PrintFormat.Int.toString
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case Builtin.ReadChar =>
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strings += PrintFormat.Char.toString
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}
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List(
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Load(
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Register(RegSize.R64, RegName.DI),
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IndexAddress(
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Register(RegSize.R64, RegName.IP),
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LabelArg(s".L.str${strings.size - 1}")
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)
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),
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Load(Register(RegSize.R64, RegName.SI), dest)
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) ++
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// alignStack() ++
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List(assemblyIR.Call(CLibFunc.Scanf))
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}
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def accessVar(ident: Ident)(using stack: LinkedHashMap[Ident, Int]): IndexAddress =
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IndexAddress(Register(RegSize.R64, RegName.SP), (stack.size - stack(ident)) * 16)
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def alignStack()(using stack: LinkedHashMap[Ident, Int]): List[AsmLine] = {
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List(
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And(Register(RegSize.R64, RegName.SP), ImmediateVal(-16))
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)
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}
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// Missing a sub instruction but dont think we need it
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def funcPrologue(): List[AsmLine] = {
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List(
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Push(Register(RegSize.R64, RegName.BP)),
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Move(Register(RegSize.R64, RegName.BP), Register(RegSize.R64, RegName.SP))
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)
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}
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def funcEpilogue(): List[AsmLine] = {
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List(
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Move(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
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Move(Register(RegSize.R64, RegName.SP), Register(RegSize.R64, RegName.BP)),
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Pop(Register(RegSize.R64, RegName.BP))
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)
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}
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// def saveRegs(regList: List[Register]): List[AsmLine] = regList.map(Push(_))
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// def restoreRegs(regList: List[Register]): List[AsmLine] = regList.reverse.map(Pop(_))
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// TODO: refactor, really ugly function
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def printF(expr: Expr)(using
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stack: LinkedHashMap[Ident, Int],
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strings: ListBuffer[String]
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): List[AsmLine] = {
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// determine the format string
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expr.ty match {
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case KnownType.String =>
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strings += PrintFormat.String.toString
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case KnownType.Char =>
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strings += PrintFormat.Char.toString
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case KnownType.Int =>
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strings += PrintFormat.Int.toString
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case _ =>
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strings += PrintFormat.String.toString
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}
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List(
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Load(
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Register(RegSize.R64, RegName.DI),
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IndexAddress(
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Register(RegSize.R64, RegName.IP),
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LabelArg(s".L.str${strings.size - 1}")
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)
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)
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)
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++
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// determine the actual value to print
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(if (expr.ty == KnownType.Bool) {
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expr match {
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case BoolLiter(true) => {
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strings += "true"
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}
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case _ => {
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strings += "false"
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}
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}
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List(
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Load(
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Register(RegSize.R64, RegName.DI),
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IndexAddress(
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Register(RegSize.R64, RegName.IP),
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LabelArg(s".L.str${strings.size - 1}")
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)
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)
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)
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} else {
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evalExprIntoReg(expr, Register(RegSize.R64, RegName.SI))
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})
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// print the value
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++
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List(
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assemblyIR.Call(CLibFunc.PrintF),
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Move(Register(RegSize.R64, RegName.DI), ImmediateVal(0)),
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assemblyIR.Call(CLibFunc.Fflush)
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)
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}
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// prints a new line
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def printLn()(using
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stack: LinkedHashMap[Ident, Int],
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strings: ListBuffer[String]
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): List[AsmLine] = {
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strings += ""
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Load(
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Register(RegSize.R64, RegName.DI),
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IndexAddress(
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Register(RegSize.R64, RegName.IP),
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LabelArg(s".L.str${strings.size - 1}")
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)
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)
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::
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List(
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assemblyIR.Call(CLibFunc.Puts),
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Move(Register(RegSize.R64, RegName.DI), ImmediateVal(0)),
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assemblyIR.Call(CLibFunc.Fflush)
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)
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}
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}
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