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refactor: merge MemLocation with IndexedAddress #37

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gk1623 merged 7 commits from single-memlocation into master 2025-02-28 18:44:49 +00:00
Conversation 8 Commits 7 Files Changed 6 +89 -64
6 changed files with 89 additions and 64 deletions
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Showing only changes of commit 37812fb5a7 - Show all commits

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src/main/wacc/backend/asmGenerator.scala
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@@ -161,15 +161,15 @@ object asmGenerator {
labelGenerator: LabelGenerator labelGenerator: LabelGenerator
): Chain[AsmLine] = { ): Chain[AsmLine] = {
var asm = Chain.empty[AsmLine] var asm = Chain.empty[AsmLine]
asm += Comment(stmt.toString)
stmt match { stmt match {
case Assign(lhs, rhs) => case Assign(lhs, rhs) =>
lhs match { lhs match {
case ident: Ident => case ident: Ident =>
if (!stack.contains(ident)) asm += stack.reserve(ident) if (!stack.contains(ident)) asm += stack.reserve(ident)
val dest = Register(ident.ty.size, AX)
asm ++= evalExprOntoStack(rhs) asm ++= evalExprOntoStack(rhs)
asm += stack.pop(RAX) asm += stack.pop(RAX)
asm += Move(stack.accessVar(ident), dest) asm += Move(stack.accessVar(ident).copy(opSize = Some(Size.Q64)), RAX)
case ArrayElem(x, i) => case ArrayElem(x, i) =>
asm ++= evalExprOntoStack(rhs) asm ++= evalExprOntoStack(rhs)
asm ++= evalExprOntoStack(i) asm ++= evalExprOntoStack(i)