Imperial-MEng/WACC_37
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feat: x86 code generation implementation without runtime checking #29

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gk1623 merged 58 commits from asm-gen into master 2025-02-27 18:54:57 +00:00
Conversation 4 Commits 58 Files Changed 14 +601 -221
7 changed files with 601 additions and 221 deletions
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Showing only changes of commit f30cf42c4b - Show all commits

35
src/main/wacc/backend/asmGenerator.scala
View File

@@ -19,7 +19,7 @@ object asmGenerator {
val RBP = Register(RegSize.R64, RegName.BP)
val RSI = Register(RegSize.R64, RegName.SI)
val _8_BIT_MASK = 0xFF
val _8_BIT_MASK = 0xff
object labelGenerator {
var labelVal = -1
@@ -70,24 +70,22 @@ object asmGenerator {
stack: LinkedHashMap[Ident, Int],
strings: ListBuffer[String]
): List[AsmLine] = {
wrapFunc(labelGenerator.getLabel(Builtin.Exit),
wrapFunc(
labelGenerator.getLabel(Builtin.Exit),
alignStack() ++
List(Pop(RDI),
assemblyIR.Call(CLibFunc.Exit))
List(Pop(RDI), assemblyIR.Call(CLibFunc.Exit))
) ++
wrapFunc(labelGenerator.getLabel(Builtin.Printf),
wrapFunc(
labelGenerator.getLabel(Builtin.Printf),
alignStack() ++
List(assemblyIR.Call(CLibFunc.PrintF),
List(
assemblyIR.Call(CLibFunc.PrintF),
Move(RDI, ImmediateVal(0)),
assemblyIR.Call(CLibFunc.Fflush)
)
) ++
wrapFunc(labelGenerator.getLabel(Builtin.Malloc),
List()
)++
wrapFunc(labelGenerator.getLabel(Builtin.Free),
List()
)
wrapFunc(labelGenerator.getLabel(Builtin.Malloc), List()) ++
wrapFunc(labelGenerator.getLabel(Builtin.Free), List())
}
def generateStmt(
@@ -191,13 +189,15 @@ object asmGenerator {
case BoolLiter(v) => List(Push(ImmediateVal(if (v) 1 else 0)))
case NullLiter() => List(Push(ImmediateVal(0)))
case ArrayElem(value, indices) => List()
case UnaryOp(x, op) => op match {
case UnaryOp(x, op) =>
op match {
// TODO: chr and ord are TYPE CASTS. They do not change the internal value,
// but will need bound checking e.t.c.
case UnaryOperator.Chr => List()
case UnaryOperator.Ord => List()
case UnaryOperator.Len => List()
case UnaryOperator.Negate => List(
case UnaryOperator.Negate =>
List(
Negate(MemLocation(RSP, SizeDir.Word))
)
case UnaryOperator.Not =>
@@ -207,7 +207,8 @@ object asmGenerator {
)
}
case BinaryOp(x, y, op) => op match {
case BinaryOp(x, y, op) =>
op match {
case BinaryOperator.Add =>
evalExprOntoStack(x) ++
evalExprOntoStack(y) ++
@@ -269,14 +270,14 @@ object asmGenerator {
evalExprOntoStack(y) ++
List(
Pop(EAX),
And(MemLocation(RSP, SizeDir.Word), EAX),
And(MemLocation(RSP, SizeDir.Word), EAX)
)
case BinaryOperator.Or =>
evalExprOntoStack(x) ++
evalExprOntoStack(y) ++
List(
Pop(EAX),
Or(MemLocation(RSP, SizeDir.Word), EAX),
Or(MemLocation(RSP, SizeDir.Word), EAX)
)
}
case microWacc.Call(target, args) => List()

14
src/main/wacc/backend/assemblyIR.scala
View File

@@ -19,7 +19,8 @@ object assemblyIR {
}
enum RegName {
case AX, AL, BX, CX, DX, SI, DI, SP, BP, IP, Reg8, Reg9, Reg10, Reg11, Reg12, Reg13, Reg14, Reg15
case AX, AL, BX, CX, DX, SI, DI, SP, BP, IP, Reg8, Reg9, Reg10, Reg11, Reg12, Reg13, Reg14,
Reg15
override def toString = this match {
case AX => "ax"
case AL => "al"
@@ -63,13 +64,20 @@ object assemblyIR {
case class Register(size: RegSize, name: RegName) extends Dest with Src {
override def toString = s"${size}${name}"
}
case class MemLocation(pointer: Long | Register, opSize: SizeDir = SizeDir.Unspecified) extends Dest with Src {
case class MemLocation(pointer: Long | Register, opSize: SizeDir = SizeDir.Unspecified)
extends Dest
with Src {
override def toString = pointer match {
case hex: Long => opSize.toString + f"[0x$hex%X]"
case reg: Register => opSize.toString + s"[$reg]"
}
}
case class IndexAddress(base: Register, offset: Int | LabelArg, opSize: SizeDir = SizeDir.Unspecified) extends Dest with Src {
case class IndexAddress(
base: Register,
offset: Int | LabelArg,
opSize: SizeDir = SizeDir.Unspecified
) extends Dest
with Src {
override def toString = s"$opSize[$base + $offset]"
}