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feat: x86 code generation implementation without runtime checking #29

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gk1623 merged 58 commits from asm-gen into master 2025-02-27 18:54:57 +00:00
Conversation 4 Commits 58 Files Changed 14 +181 -16
3 changed files with 181 additions and 16 deletions
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14
src/test/wacc/instructionSpec.scala
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@@ -3,28 +3,28 @@ import wacc.assemblyIR._
class instructionSpec extends AnyFunSuite {
val named64BitRegister = Register.Named("ax", RegSize.R64)
val named64BitRegister = Register(RegSize.R64, RegName.AX)
test("named 64-bit register toString") {
assert(named64BitRegister.toString == "rax")
}
val named32BitRegister = Register.Named("ax", RegSize.E32)
val named32BitRegister = Register(RegSize.E32, RegName.AX)
test("named 32-bit register toString") {
assert(named32BitRegister.toString == "eax")
}
val scratch64BitRegister = Register.Scratch(1, RegSize.R64)
val scratch64BitRegister = Register(RegSize.R64, RegName.Reg8)
test("scratch 64-bit register toString") {
assert(scratch64BitRegister.toString == "r1")
assert(scratch64BitRegister.toString == "r8")
}
val scratch32BitRegister = Register.Scratch(1, RegSize.E32)
val scratch32BitRegister = Register(RegSize.E32, RegName.Reg8)
test("scratch 32-bit register toString") {
assert(scratch32BitRegister.toString == "r1d")
assert(scratch32BitRegister.toString == "e8")
}
val memLocationWithHex = MemLocation(0x12345678)
@@ -54,7 +54,7 @@ class instructionSpec extends AnyFunSuite {
val subInstruction = Subtract(scratch64BitRegister, named64BitRegister)
test("x86: sub instruction toString") {
assert(subInstruction.toString == "\tsub r1, rax")
assert(subInstruction.toString == "\tsub r8, rax")
}
val callInstruction = Call(CLibFunc.Scanf)