From 332c00b15b3de87e4a9efb059c0ba72939d5b044 Mon Sep 17 00:00:00 2001 From: Jonny Date: Thu, 27 Feb 2025 19:13:17 +0000 Subject: [PATCH] feat: added runtime errors class and object --- src/main/wacc/backend/RuntimeErrors.scala | 16 ++++++++++++++++ src/main/wacc/backend/asmGenerator.scala | 20 ++------------------ 2 files changed, 18 insertions(+), 18 deletions(-) create mode 100644 src/main/wacc/backend/RuntimeErrors.scala diff --git a/src/main/wacc/backend/RuntimeErrors.scala b/src/main/wacc/backend/RuntimeErrors.scala new file mode 100644 index 0000000..f457337 --- /dev/null +++ b/src/main/wacc/backend/RuntimeErrors.scala @@ -0,0 +1,16 @@ +package wacc + +import cats.data.Chain +import wacc.assemblyIR._ + +case class RuntimeError(strLabel: String, errStr: String, errLabel: String) { + def stringDef: Chain[AsmLine] = Chain( + Directive.Int(errStr.size), + LabelDef(strLabel), + Directive.Asciz(errStr) + ) +} + +object RuntimeErrors { + val zeroDivError = RuntimeError(".L._errDivZero_str0", "fatal error: division or modulo by zero", ".L._errDivZero") +} diff --git a/src/main/wacc/backend/asmGenerator.scala b/src/main/wacc/backend/asmGenerator.scala index 60e0b47..9e2772c 100644 --- a/src/main/wacc/backend/asmGenerator.scala +++ b/src/main/wacc/backend/asmGenerator.scala @@ -3,6 +3,8 @@ package wacc import scala.collection.mutable.ListBuffer import cats.data.Chain import cats.syntax.foldable._ +import wacc.RuntimeErrors._ + object asmGenerator { import microWacc._ @@ -13,24 +15,6 @@ object asmGenerator { import sizeExtensions._ import lexer.escapedChars - abstract case class Error() { - def strLabel: String - def errStr: String - def errLabel: String - - def stringDef: Chain[AsmLine] = Chain( - Directive.Int(errStr.size), - LabelDef(strLabel), - Directive.Asciz(errStr) - ) - } - object zeroDivError extends Error { - // TODO: is this bad? Can we make an error case class/some other structure? - def strLabel = ".L._errDivZero_str0" - def errStr = "fatal error: division or modulo by zero" - def errLabel = ".L._errDivZero" - } - private val RAX = Register(Q64, AX) private val EAX = Register(D32, AX) private val RDI = Register(Q64, DI)