refactor: merge MemLocation with IndexedAddress

This commit is contained in:
2025-02-28 16:26:40 +00:00
parent 61643a49eb
commit 1a39950a7b
5 changed files with 62 additions and 40 deletions

View File

@@ -97,22 +97,33 @@ object assemblyIR {
}
}
case class MemLocation(pointer: Register, opSize: Size) extends Dest with Src {
override def toString =
opSize.toString + s"[$pointer]"
}
case class IndexAddress(
case class MemLocation(
base: Register,
offset: Int | LabelArg,
indexReg: Register = Register(Size.Q64, RegName.AX),
scale: Int = 0
offset: Int | LabelArg = 0,
// scale 0 will make register irrelevant, no other reason as to why it's RAX
scaledIndex: (Register, Int) = (Register(Size.Q64, RegName.AX), 0),
opSize: Option[Size] = None
) extends Dest
with Src {
override def toString = if (scale != 0) {
s"[$base + $indexReg * $scale + $offset]"
} else {
s"[$base + $offset]"
def copy(
base: Register = this.base,
offset: Int | LabelArg = this.offset,
scaledIndex: (Register, Int) = this.scaledIndex,
opSize: Option[Size] = this.opSize
): MemLocation = MemLocation(base, offset, scaledIndex, opSize)
override def toString(): String = {
val opSizeStr = opSize.map(_.toString).getOrElse("")
val baseStr = base.toString
val offsetStr = offset match {
case 0 => ""
case off => s" + $off"
}
val scaledIndexStr = scaledIndex match {
case (reg, scale) if scale != 0 => s" + $reg * $scale"
case _ => ""
}
s"$opSizeStr[$baseStr$scaledIndexStr$offsetStr]"
}
}
@@ -145,8 +156,7 @@ object assemblyIR {
case class Pop(op1: Src) extends Operation("pop", op1)
// move operations
case class Move(op1: Dest, op2: Src) extends Operation("mov", op1, op2)
case class Load(op1: Register, op2: MemLocation | IndexAddress)
extends Operation("lea ", op1, op2)
case class Load(op1: Register, op2: MemLocation) extends Operation("lea ", op1, op2)
// function call operations
case class Call(op1: CLibFunc | LabelArg) extends Operation("call", op1)