Imperial-MEng/WACC_37
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

feat: implements binary operators in asmGenerator

Browse Source 
Co-authored-by: Gleb Koval <gleb@koval.net>
Co-authored-by: Barf-Vader <Barf-Vader@users.noreply.github.com>
This commit is contained in:
Guy C
2025-02-25 00:00:12 +00:00
parent 668d7338ae
commit 1488281223
4 changed files with 285 additions and 109 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
src/main/wacc/backend/assemblyIR.scala
View File

@@ -9,17 +9,20 @@ object assemblyIR {
enum RegSize {
case R64
case E32
case Byte
override def toString = this match {
case R64 => "r"
case E32 => "e"
case Byte => ""
}
}
enum RegName {
case AX, BX, CX, DX, SI, DI, SP, BP, IP, Reg8, Reg9, Reg10, Reg11, Reg12, Reg13, Reg14, Reg15
case AX, AL, BX, CX, DX, SI, DI, SP, BP, IP, Reg8, Reg9, Reg10, Reg11, Reg12, Reg13, Reg14, Reg15
override def toString = this match {
case AX => "ax"
case AL => "al"
case BX => "bx"
case CX => "cx"
case DX => "dx"
@@ -42,7 +45,6 @@ object assemblyIR {
// arguments
enum CLibFunc extends Operand {
case Scanf,
Puts,
Fflush,
Exit,
PrintF
@@ -51,24 +53,24 @@ object assemblyIR {
override def toString = this match {
case Scanf => "scanf" + plt
case Puts => "puts" + plt
case Fflush => "fflush" + plt
case Exit => "exit" + plt
case PrintF => "printf" + plt
}
}
//TODO register naming conventions are wrong
case class Register(size: RegSize, name: RegName) extends Dest with Src {
override def toString = s"${size}${name}"
}
case class MemLocation(pointer: Long | Register) extends Dest with Src {
case class MemLocation(pointer: Long | Register, opSize: SizeDir = SizeDir.Unspecified) extends Dest with Src {
override def toString = pointer match {
case hex: Long => f"[0x$hex%X]"
case reg: Register => s"[$reg]"
case hex: Long => opSize.toString + f"[0x$hex%X]"
case reg: Register => opSize.toString + s"[$reg]"
}
}
case class IndexAddress(base: Register, offset: Int | LabelArg) extends Dest with Src {
override def toString = s"[$base + $offset]"
case class IndexAddress(base: Register, offset: Int | LabelArg, opSize: SizeDir = SizeDir.Unspecified) extends Dest with Src {
override def toString = s"$opSize[$base + $offset]"
}
case class ImmediateVal(value: Int) extends Src {
@@ -85,11 +87,13 @@ object assemblyIR {
}
case class Add(op1: Dest, op2: Src) extends Operation("add", op1, op2)
case class Subtract(op1: Dest, op2: Src) extends Operation("sub", op1, op2)
case class Multiply(ops: Operand*) extends Operation("mul", ops*)
case class Divide(op1: Src) extends Operation("div", op1)
case class Multiply(ops: Operand*) extends Operation("imul", ops*)
case class Divide(op1: Src) extends Operation("idiv", op1)
case class Negate(op: Dest) extends Operation("neg", op)
case class And(op1: Dest, op2: Src) extends Operation("and", op1, op2)
case class Or(op1: Dest, op2: Src) extends Operation("or", op1, op2)
case class Xor(op1: Dest, op2: Src) extends Operation("xor", op1, op2)
case class Compare(op1: Dest, op2: Src) extends Operation("cmp", op1, op2)
// stack operations
@@ -106,6 +110,9 @@ object assemblyIR {
case class Jump(op1: LabelArg, condition: Cond = Cond.Always)
extends Operation(s"j${condition.toString}", op1)
case class Set(op1: Dest, condition: Cond = Cond.Always)
extends Operation(s"set${condition.toString}", op1)
case class LabelDef(name: String) extends AsmLine {
override def toString = s"$name:"
}
@@ -156,4 +163,16 @@ object assemblyIR {
case String => "%s"
}
}
}
enum SizeDir {
case Byte, Word, Unspecified
private val ptr = "ptr "
override def toString(): String = this match {
case Byte => "byte " + ptr
case Word => "word " + ptr
case Unspecified => ""
}
}
}