feat: implements binary operators in asmGenerator
Co-authored-by: Gleb Koval <gleb@koval.net> Co-authored-by: Barf-Vader <Barf-Vader@users.noreply.github.com>
This commit is contained in:
Guy C
@@ -2,19 +2,37 @@ package wacc
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import scala.collection.mutable.LinkedHashMap
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import scala.collection.mutable.ListBuffer
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import cats.syntax.align
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object labelGenerator {
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var labelVal = -1
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def getLabel(): String = {
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labelVal += 1
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s".L$labelVal"
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}
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}
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object asmGenerator {
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import microWacc._
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import assemblyIR._
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import wacc.types._
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val RAX = Register(RegSize.R64, RegName.AX)
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val EAX = Register(RegSize.E32, RegName.AX)
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val RSP = Register(RegSize.R64, RegName.SP)
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val ESP = Register(RegSize.E32, RegName.SP)
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val EDX = Register(RegSize.E32, RegName.DX)
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val RDI = Register(RegSize.R64, RegName.DI)
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val RIP = Register(RegSize.R64, RegName.IP)
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val RBP = Register(RegSize.R64, RegName.BP)
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val RSI = Register(RegSize.R64, RegName.SI)
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val _8_BIT_MASK = 0xFF
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object labelGenerator {
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var labelVal = -1
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def getLabel(): String = {
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labelVal += 1
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s".L$labelVal"
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}
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def getLabel(target: CallTarget): String = target match{
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case Ident(v,_) => s"wacc_$v"
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case Builtin(name) => s"_$name"
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}
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}
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def generateAsm(microProg: Program): List[AsmLine] = {
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given stack: LinkedHashMap[Ident, Int] = LinkedHashMap[Ident, Int]()
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given strings: ListBuffer[String] = ListBuffer[String]()
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@@ -25,10 +43,8 @@ object asmGenerator {
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funcPrologue() ++
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alignStack() ++
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main.flatMap(generateStmt) ++
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List(Move(Register(RegSize.R64, RegName.AX), ImmediateVal(0))) ++
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funcEpilogue() ++
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List(assemblyIR.Return()) ++
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generateFuncs()
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List(Move(RAX, ImmediateVal(0))) ++
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funcEpilogue()
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val strDirs = strings.toList.zipWithIndex.flatMap { case (str, i) =>
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List(Directive.Int(str.size), LabelDef(s".L.str$i"), Directive.Asciz(str))
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@@ -40,12 +56,38 @@ object asmGenerator {
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progAsm
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}
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//TODO
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def generateFuncs()(using
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def wrapFunc(labelName: String, funcBody: List[AsmLine])(using
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stack: LinkedHashMap[Ident, Int],
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strings: ListBuffer[String]
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): List[AsmLine] = {
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LabelDef(labelName) ::
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funcPrologue() ++
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funcBody ++
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funcEpilogue()
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}
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def generateBuiltInFuncs()(using
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stack: LinkedHashMap[Ident, Int],
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strings: ListBuffer[String]
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): List[AsmLine] = {
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wrapFunc(labelGenerator.getLabel(Builtin.Exit),
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alignStack() ++
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List(Pop(RDI),
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assemblyIR.Call(CLibFunc.Exit))
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) ++
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wrapFunc(labelGenerator.getLabel(Builtin.Printf),
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alignStack() ++
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List(assemblyIR.Call(CLibFunc.PrintF),
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Move(RDI, ImmediateVal(0)),
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assemblyIR.Call(CLibFunc.Fflush)
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)
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)++
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wrapFunc(labelGenerator.getLabel(Builtin.Malloc),
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List()
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)++
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wrapFunc(labelGenerator.getLabel(Builtin.Free),
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List()
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)
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}
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def generateStmt(
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@@ -53,28 +95,16 @@ object asmGenerator {
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)(using stack: LinkedHashMap[Ident, Int], strings: ListBuffer[String]): List[AsmLine] =
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stmt match {
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case microWacc.Call(Builtin.Exit, code :: _) =>
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// alignStack() ++
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evalExprIntoReg(code, Register(RegSize.R64, RegName.DI)) ++
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List(assemblyIR.Call(CLibFunc.Exit))
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case microWacc.Call(Builtin.Println, expr :: _) =>
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// alignStack() ++
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printF(expr) ++
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printLn()
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case microWacc.Call(Builtin.Print, expr :: _) =>
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// alignStack() ++
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printF(expr)
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List()
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case Assign(lhs, rhs) =>
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var dest: IndexAddress =
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IndexAddress(Register(RegSize.R64, RegName.SP), 0) // gets overrwitten
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IndexAddress(RSP, 0) // gets overrwitten
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(lhs match {
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case ident: Ident =>
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if (!stack.contains(ident)) {
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stack += (ident -> (stack.size + 1))
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dest = accessVar(ident)
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List(Subtract(Register(RegSize.R64, RegName.SP), ImmediateVal(16)))
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List(Subtract(RSP, ImmediateVal(8)))
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} else {
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dest = accessVar(ident)
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List()
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@@ -90,15 +120,16 @@ object asmGenerator {
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case microWacc.Call(Builtin.ReadChar, _) =>
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readIntoVar(dest, Builtin.ReadChar)
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case _ =>
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evalExprIntoReg(rhs, Register(RegSize.R64, RegName.AX)) ++
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List(Move(dest, Register(RegSize.R64, RegName.AX)))
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evalExprOntoStack(rhs) ++
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List(Pop(dest))
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})
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case If(cond, thenBranch, elseBranch) => {
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val elseLabel = labelGenerator.getLabel()
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val endLabel = labelGenerator.getLabel()
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evalExprIntoReg(cond, Register(RegSize.R64, RegName.AX)) ++
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evalExprOntoStack(cond) ++
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List(
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Compare(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
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Compare(MemLocation(RSP, SizeDir.Word), ImmediateVal(0)),
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Add(RSP, ImmediateVal(8)),
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Jump(LabelArg(elseLabel), Cond.Equal)
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) ++
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thenBranch.flatMap(generateStmt) ++
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@@ -110,30 +141,33 @@ object asmGenerator {
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val startLabel = labelGenerator.getLabel()
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val endLabel = labelGenerator.getLabel()
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List(LabelDef(startLabel)) ++
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evalExprIntoReg(cond, Register(RegSize.R64, RegName.AX)) ++
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evalExprOntoStack(cond) ++
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List(
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Compare(Register(RegSize.R64, RegName.AX), ImmediateVal(0)),
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Compare(MemLocation(RSP, SizeDir.Word), ImmediateVal(0)),
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Add(RSP, ImmediateVal(8)),
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Jump(LabelArg(endLabel), Cond.Equal)
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) ++
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body.flatMap(generateStmt) ++
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List(Jump(LabelArg(startLabel)), LabelDef(endLabel))
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}
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case microWacc.Return(expr) =>
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evalExprIntoReg(expr, Register(RegSize.R64, RegName.AX))
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evalExprOntoStack(expr) ++
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List(Pop(RAX), assemblyIR.Return())
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case _ => List()
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}
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def evalExprIntoReg(expr: Expr, dest: Register)(using
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def evalExprOntoStack(expr: Expr)(using
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stack: LinkedHashMap[Ident, Int],
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strings: ListBuffer[String]
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): List[AsmLine] = {
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expr match {
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case IntLiter(v) =>
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List(Move(dest, ImmediateVal(v)))
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List(Push(ImmediateVal(v)))
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case CharLiter(v) =>
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List(Move(dest, ImmediateVal(v.toInt)))
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List(Push(ImmediateVal(v.toInt)))
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case ident: Ident =>
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List(Move(dest, accessVar(ident)))
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List(Push(accessVar(ident)))
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case ArrayLiter(elems) =>
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expr.ty match {
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case KnownType.String =>
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@@ -143,70 +177,173 @@ object asmGenerator {
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}.mkString
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List(
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Load(
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dest,
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RAX,
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IndexAddress(
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Register(RegSize.R64, RegName.IP),
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RIP,
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LabelArg(s".L.str${strings.size - 1}")
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)
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)
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),
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Push(RAX)
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)
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// TODO other array types
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case _ => List()
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}
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// TODO other expr types
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case BoolLiter(v) => List(Move(dest, ImmediateVal(if (v) 1 else 0)))
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case _ => List()
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case BoolLiter(v) => List(Push(ImmediateVal(if (v) 1 else 0)))
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case NullLiter() => List(Push(ImmediateVal(0)))
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case ArrayElem(value, indices) => List()
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case UnaryOp(x, op) => op match {
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// TODO: chr and ord are TYPE CASTS. They do not change the internal value,
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// but will need bound checking e.t.c.
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case UnaryOperator.Chr => List()
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case UnaryOperator.Ord => List()
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case UnaryOperator.Len => List()
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case UnaryOperator.Negate => List(
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Negate(MemLocation(RSP,SizeDir.Word))
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)
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case UnaryOperator.Not =>
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evalExprOntoStack(x) ++
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List(
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Xor(MemLocation(RSP, SizeDir.Word), ImmediateVal(1))
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)
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}
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case BinaryOp(x, y, op) => op match {
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case BinaryOperator.Add =>
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evalExprOntoStack(x) ++
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evalExprOntoStack(y) ++
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List(
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Pop(EAX),
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Add(MemLocation(RSP, SizeDir.Word), EAX)
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// TODO OVERFLOWING
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)
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case BinaryOperator.Sub =>
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evalExprOntoStack(x) ++
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evalExprOntoStack(y) ++
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List(
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Pop(EAX),
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Subtract(MemLocation(RSP, SizeDir.Word), EAX)
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// TODO OVERFLOWING
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)
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case BinaryOperator.Mul =>
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evalExprOntoStack(x) ++
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evalExprOntoStack(y) ++
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List(
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Pop(EAX),
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Multiply(MemLocation(RSP, SizeDir.Word), EAX)
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// TODO OVERFLOWING
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)
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case BinaryOperator.Div =>
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evalExprOntoStack(y) ++
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evalExprOntoStack(x) ++
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List(
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Pop(EAX),
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Divide(MemLocation(RSP, SizeDir.Word)),
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Add(RSP, ImmediateVal(8)),
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Push(EAX)
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// TODO CHECK DIVISOR IS NOT 0
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)
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case BinaryOperator.Mod =>
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evalExprOntoStack(y) ++
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evalExprOntoStack(x) ++
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List(
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Pop(EAX),
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Divide(MemLocation(RSP, SizeDir.Word)),
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Add(RSP, ImmediateVal(8)),
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Push(EDX)
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// TODO CHECK DIVISOR IS NOT 0
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)
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case BinaryOperator.Eq =>
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generateComparison(x, y, Cond.Equal)
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case BinaryOperator.Neq =>
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generateComparison(x, y, Cond.NotEqual)
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case BinaryOperator.Greater =>
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generateComparison(x, y, Cond.Greater)
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case BinaryOperator.GreaterEq =>
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generateComparison(x, y, Cond.GreaterEqual)
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case BinaryOperator.Less =>
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generateComparison(x, y, Cond.Less)
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case BinaryOperator.LessEq =>
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generateComparison(x, y, Cond.LessEqual)
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case BinaryOperator.And =>
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evalExprOntoStack(x) ++
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evalExprOntoStack(y) ++
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List(
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Pop(EAX),
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And(MemLocation(RSP, SizeDir.Word), EAX),
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)
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case BinaryOperator.Or =>
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evalExprOntoStack(x) ++
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evalExprOntoStack(y) ++
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List(
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Pop(EAX),
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Or(MemLocation(RSP, SizeDir.Word), EAX),
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)
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}
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case microWacc.Call(target, args) => List()
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}
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}
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// TODO make sure EOF doenst override the value in the stack
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// probably need labels implemented for conditional jumps
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def readIntoVar(dest: IndexAddress, readType: Builtin.ReadInt.type | Builtin.ReadChar.type)(using
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// def readIntoVar(dest: IndexAddress, readType: Builtin.ReadInt.type | Builtin.ReadChar.type)(using
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// stack: LinkedHashMap[Ident, Int],
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// strings: ListBuffer[String]
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// ): List[AsmLine] = {
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// readType match {
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// case Builtin.ReadInt =>
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// strings += PrintFormat.Int.toString
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// case Builtin.ReadChar =>
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// strings += PrintFormat.Char.toString
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// }
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// List(
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// Load(
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// RDI,
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// IndexAddress(
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// RIP,
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// LabelArg(s".L.str${strings.size - 1}")
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// )
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// ),
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// Load(RSI, dest)
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// ) ++
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// // alignStack() ++
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// List(assemblyIR.Call(CLibFunc.Scanf))
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// }
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def generateComparison(x : Expr, y: Expr, cond: Cond)(using
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stack: LinkedHashMap[Ident, Int],
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strings: ListBuffer[String]
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): List[AsmLine] = {
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readType match {
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case Builtin.ReadInt =>
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strings += PrintFormat.Int.toString
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case Builtin.ReadChar =>
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strings += PrintFormat.Char.toString
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}
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List(
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Load(
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Register(RegSize.R64, RegName.DI),
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IndexAddress(
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Register(RegSize.R64, RegName.IP),
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LabelArg(s".L.str${strings.size - 1}")
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)
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),
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Load(Register(RegSize.R64, RegName.SI), dest)
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) ++
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// alignStack() ++
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List(assemblyIR.Call(CLibFunc.Scanf))
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evalExprOntoStack(x) ++
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evalExprOntoStack(y) ++
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List(
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Pop(EAX),
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Compare(MemLocation(RSP, SizeDir.Word), EAX),
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Set(Register(RegSize.Byte, RegName.AL), cond),
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And(EAX, ImmediateVal(_8_BIT_MASK)),
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Push(EAX)
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)
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}
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def accessVar(ident: Ident)(using stack: LinkedHashMap[Ident, Int]): IndexAddress =
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IndexAddress(Register(RegSize.R64, RegName.SP), (stack.size - stack(ident)) * 16)
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IndexAddress(RSP, (stack.size - stack(ident)) * 8)
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def alignStack()(using stack: LinkedHashMap[Ident, Int]): List[AsmLine] = {
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List(
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And(Register(RegSize.R64, RegName.SP), ImmediateVal(-16))
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And(RSP, ImmediateVal(-16))
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)
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}
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// Missing a sub instruction but dont think we need it
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def funcPrologue(): List[AsmLine] = {
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List(
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Push(Register(RegSize.R64, RegName.BP)),
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Move(Register(RegSize.R64, RegName.BP), Register(RegSize.R64, RegName.SP))
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Push(RBP),
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Move(RBP, RSP)
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)
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}
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def funcEpilogue(): List[AsmLine] = {
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List(
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Move(Register(RegSize.R64, RegName.SP), Register(RegSize.R64, RegName.BP)),
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Pop(Register(RegSize.R64, RegName.BP))
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Move(RSP, RBP),
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Pop(RBP),
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assemblyIR.Return()
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)
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}
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@@ -231,9 +368,9 @@ object asmGenerator {
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}
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List(
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Load(
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Register(RegSize.R64, RegName.DI),
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RDI,
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IndexAddress(
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Register(RegSize.R64, RegName.IP),
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RIP,
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LabelArg(s".L.str${strings.size - 1}")
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)
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)
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@@ -251,22 +388,23 @@ object asmGenerator {
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}
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List(
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Load(
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Register(RegSize.R64, RegName.DI),
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RDI,
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IndexAddress(
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Register(RegSize.R64, RegName.IP),
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RIP,
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LabelArg(s".L.str${strings.size - 1}")
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)
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)
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)
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} else {
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evalExprIntoReg(expr, Register(RegSize.R64, RegName.SI))
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evalExprOntoStack(expr) ++
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List(Pop(RSI))
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})
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// print the value
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++
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List(
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assemblyIR.Call(CLibFunc.PrintF),
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Move(Register(RegSize.R64, RegName.DI), ImmediateVal(0)),
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Move(RDI, ImmediateVal(0)),
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assemblyIR.Call(CLibFunc.Fflush)
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)
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}
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@@ -278,16 +416,16 @@ object asmGenerator {
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): List[AsmLine] = {
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strings += ""
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Load(
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Register(RegSize.R64, RegName.DI),
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RDI,
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IndexAddress(
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Register(RegSize.R64, RegName.IP),
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RIP,
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LabelArg(s".L.str${strings.size - 1}")
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)
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)
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::
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List(
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assemblyIR.Call(CLibFunc.Puts),
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Move(Register(RegSize.R64, RegName.DI), ImmediateVal(0)),
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Move(RDI, ImmediateVal(0)),
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assemblyIR.Call(CLibFunc.Fflush)
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)
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