fix: zero-out D32 as well
This commit is contained in:
@@ -174,7 +174,7 @@ object asmGenerator {
|
|||||||
asm ++= evalExprOntoStack(rhs)
|
asm ++= evalExprOntoStack(rhs)
|
||||||
asm ++= evalExprOntoStack(i)
|
asm ++= evalExprOntoStack(i)
|
||||||
asm += stack.pop(RCX)
|
asm += stack.pop(RCX)
|
||||||
asm += Compare(ECX, ImmediateVal(0))
|
asm += Compare(RCX, ImmediateVal(0))
|
||||||
asm += Jump(labelGenerator.getLabelArg(OutOfBoundsError), Cond.Less)
|
asm += Jump(labelGenerator.getLabelArg(OutOfBoundsError), Cond.Less)
|
||||||
asm += stack.push(KnownType.Int.size, RCX)
|
asm += stack.push(KnownType.Int.size, RCX)
|
||||||
asm ++= evalExprOntoStack(x)
|
asm ++= evalExprOntoStack(x)
|
||||||
@@ -461,8 +461,8 @@ object asmGenerator {
|
|||||||
|
|
||||||
def stackAlign: AsmLine = And(Register(Size.Q64, SP), ImmediateVal(-16))
|
def stackAlign: AsmLine = And(Register(Size.Q64, SP), ImmediateVal(-16))
|
||||||
private def zeroRest(dest: Dest, size: Size): Chain[AsmLine] = size match {
|
private def zeroRest(dest: Dest, size: Size): Chain[AsmLine] = size match {
|
||||||
case Size.Q64 | Size.D32 => Chain.empty
|
case Size.Q64 => Chain.empty
|
||||||
case _ => Chain.one(And(dest, ImmediateVal((1 << (size.toInt * 8)) - 1)))
|
case _ => Chain.one(And(dest, ImmediateVal(((BigInt(1) << (size.toInt * 8)) - 1).toInt)))
|
||||||
}
|
}
|
||||||
|
|
||||||
private val escapedCharsMapping = escapedChars.map { case (k, v) => v -> s"\\$k" }
|
private val escapedCharsMapping = escapedChars.map { case (k, v) => v -> s"\\$k" }
|
||||||
|
|||||||
Reference in New Issue
Block a user