Imperial-MEng/WACC_37
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feat: implemented println and exit

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This commit is contained in:
Barf-Vader
2025-02-21 22:53:20 +00:00
parent 67f7e64b95
commit 02e741c52e
2 changed files with 158 additions and 9 deletions
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56
src/main/wacc/backend/assemblyIR.scala
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@@ -16,6 +16,29 @@ object assemblyIR {
}
}
enum RegName {
case AX, BX, CX, DX, SI, DI, SP, BP, IP, Reg8, Reg9, Reg10, Reg11, Reg12, Reg13, Reg14, Reg15
override def toString = this match {
case AX => "ax"
case BX => "bx"
case CX => "cx"
case DX => "dx"
case SI => "si"
case DI => "di"
case SP => "sp"
case BP => "bp"
case IP => "ip"
case Reg8 => "8"
case Reg9 => "9"
case Reg10 => "10"
case Reg11 => "11"
case Reg12 => "12"
case Reg13 => "13"
case Reg14 => "14"
case Reg15 => "15"
}
}
// arguments
enum CLibFunc extends Operand {
case Scanf,
@@ -35,13 +58,8 @@ object assemblyIR {
}
}
enum Register extends Dest with Src {
case Named(name: String, size: RegSize)
case Scratch(num: Int, size: RegSize)
override def toString = this match {
case Named(name, size) => s"${size}${name.toLowerCase()}"
case Scratch(num, size) => s"r${num}${if (size == RegSize.E32) "d" else ""}"
}
case class Register(size: RegSize, name: RegName) extends Dest with Src {
override def toString = s"${size}${name}"
}
case class MemLocation(pointer: Long | Register) extends Dest with Src {
override def toString = pointer match {
@@ -49,6 +67,9 @@ object assemblyIR {
case reg: Register => s"[$reg]"
}
}
case class IndexAddress(base: Register, offset: Int | LabelArg) extends Dest with Src {
override def toString = s"[$base + $offset]"
}
case class ImmediateVal(value: Int) extends Src {
override def toString = value.toString
@@ -74,10 +95,10 @@ object assemblyIR {
// stack operations
case class Push(op1: Src) extends Operation("push", op1)
case class Pop(op1: Src) extends Operation("pop", op1)
case class Call(op1: CLibFunc) extends Operation("call", op1)
case class Call(op1: CLibFunc | LabelArg) extends Operation("call", op1)
case class Move(op1: Dest, op2: Src) extends Operation("mov", op1, op2)
case class Load(op1: Register, op2: MemLocation) extends Operation("lea ", op1, op2)
case class Load(op1: Register, op2: MemLocation | IndexAddress) extends Operation("lea ", op1, op2)
case class Return() extends Operation("ret")
@@ -108,4 +129,21 @@ object assemblyIR {
case Always => "mp"
}
}
enum Directive extends AsmLine {
case IntelSyntax, RoData, Text
case Global(name: String)
case Int(value: scala.Int)
case Asciz(string: String)
override def toString(): String = this match {
case IntelSyntax => ".intel_syntax noprefix"
case Global(name) => s".globl $name"
case Text => ".text"
case RoData => ".section .rodata"
case Int(value) => s".int $value"
case Asciz(string) => s".asciz $string"
}
}
}